CDK8307 Cadeka Microcircuits LLC., CDK8307 Datasheet - Page 20

• Manufacturer Part Number: CDK8307
• Description: 12/13-bit, 20/40/50/65/80msps, Eight Channel, Ultra Low Power Adc With Lvds
• Manufacturer: Cadeka Microcircuits LLC.

PRELIMINARY Data Sheet
Table 10. LVDS Test Patterns
To ease the LVDS synchronization setup of CDK8307, several test patterns can be set up on the outputs. Normal ADC
data are replaced by the test pattern in these modes. Setting en_ramp to '1' sets up a repeating full-scale ramp pattern
on all data outputs. The ramp starts at code zero and is increased 1LSB every clock cycle. It returns to zero code and
starts the ramp again after reaching the full-scale code.
A constant value can be set up on the outputs by setting single_custom_pat to '1', and programming the desired value
in bits_custom1<13:0> . In this mode, bits_custom1<13:0> replaces the ADC data at the output, and is controlled by
LSB-first and MSB-first modes in the same way as normal ADC data are.
The device may also be made to alternate between two codes by programming dual_custom_pat to '1'. The two codes
are the contents of bits_custom1<13:0> and bits_custom2<13:0>. Two preset patterns can also be selected:
Note: Only one of the above patterns should be selected at the same time.
Table 11. Programmable Gain
CDK8307 includes a purely digital programmable gain option in addition to the Full-scale Control. The programmable
gain of each channel can be individually set using a set of four bits, indicated as gain_chn<3:0> for Channel x. The gain
setting is coded in binary from 0dB to 12dB, as shown in Table 12 on the following page.
©2009 CADEKA Microcircuits LLC
en_ramp
dual_custom_pat
single_custom_
pat
bits_cus-
tom1<13:0>
bits_cus-
tom2<13:0>
pat_deskew
pat_sync
gain_ch1<3:0>
gain_ch2<3:0>
gain_ch3<3:0>
gain_ch4<3:0>
gain_ch5<3:0>
gain_ch6<3:0>
gain_ch7<3:0>
gain_ch8<3:0>
1. Deskew pattern: Set using pat_deskew, this mode replaces the ADC output with '01010101010101' (two LSBs
2. Sync pattern: Set using pat_sync, the normal ADC word is replaced by a fixed 1111110000000 word.
Name
Name
removed in 12 bit mode).
Enables a repeating full-scale
ramp pattern on the outputs
Enable the mode wherein the output
toggles between two defined codes
Enables the mode wherein the
output is a constant specified code
Bits for the single custom pattern
and for the first code of the dual
custom pattern. <0> is the LSB
Bits for the second code of the
dual custom pattern
Enable deskew pattern mode
Enable sync pattern mode
Programmable gain for channel 1 0dB gain
Programmable gain for channel 2 0dB gain
Programmable gain for channel 3 0dB gain
Programmable gain for channel 4 0dB gain
Programmable gain for channel 5 0dB gain
Programmable gain for channel 6 0dB gain
Programmable gain for channel 7 0dB gain
Programmable gain for channel 8 0dB gain
Description
Description
Inactive
Inactive
Inactive
Inactive
Inactive
Inactive
Inactive
Default
Default
5
5
D
1
X
X
D
1
X
X
D
1
4
X X X X X X X X X X X X X
X X X X X X X X X X X X X
D
1
4
X X X
X X X
D
3
D
3
1
1
D
1
2
D
1
2
D
1
D
1
1
1
X X X X
X X X X
D
1
0
D
1
0
D
9
D
9
D
D
8
8
D
7
D
7
X X X X
X X X X
D
D
6
X
0
0
6
D
5
0
X
0
D
5
D
4
0
0
X
D
4
D
D
X X X X
X X X X
3
3
D
2
D
2
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D
D
1
0
X
1
D
0
X
0
D
0
Address
Address
In Hex
In Hex
2A
2B
25
26
27
45
20