WM8608 ETC-unknow, WM8608 Datasheet - Page 17

• Manufacturer Part Number: WM8608
• Description: The Wm8608 Comprises A High Performance Multi-channel Pwm Digital Power Amplifier Controller. Simply By Adding Appropriate Power Output Stages A Multi-channel Power Amplifier May Be Built. Six Identical Full Audio Bandwidth Channels, Plus A Reduced B
• Manufacturer: ETC-unknow

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multiplexed with LRCLK indicating whether the left or right channel is present. LRCLK is also used as
a timing reference to indicate the beginning or end of the data words.
In left justified, right justified and I
times the selected word length. LRCLK must be high for a minimum of word length BCLKs and low
for a minimum of word length BCLKs. Any mark to space ratio on LRCLK is acceptable provided the
above requirements are met.
In DSP mode A or B, all channels are time multiplexed onto DINFRONT. LRCLK is used as a frame
sync signal to identify the MSB of the first word. The minimum number of BCLKs per LRCLK period
is 8 times the selected word length. Any mark to space ratio is acceptable on LRCLK provided the
rising edge is correctly positioned (see Figure 9, Figure 10 and Figure 11).
LEFT JUSTIFIED MODE
In left justified mode, the MSB is sampled on the first rising edge of BCLK following a LRCLK
transition. LRCLK is high during the left samples and low during the right samples.
Figure 9 Left Justified Mode Timing Diagram
RIGHT JUSTIFIED MODE
In right justified mode, the LSB is sampled on the rising edge of BCLK preceding a LRCLK transition.
LRCLK is high during the left samples and low during the right samples.
Figure 10 Right Justified Mode Timing Diagram
DINFRONT
DINFRONT
DINC_LFE
DINC_LFE
DINSRND
DINREAR
DINSRND
DINREAR
LRCLK
LRCLK
BCLK
BCLK
MSB
1
2
3
MSB
1
LEFT CHANNEL
LEFT CHANNEL
2
2
3
S modes, the minimum number of BCLKs per DACLRC period is 2
n-2 n-1
n
LSB
n-2 n-1
LSB
MSB
1/fs
n
1/fs
1
2
3
MSB
1
RIGHT CHANNEL
RIGHT CHANNEL
2
3
n-2 n-1
PP Rev 1.5 March 2004
n
LSB
n-2 n-1
WM8608
LSB
n
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