ADT7475 Analog Devices, Inc., ADT7475 Datasheet - Page 24

• Manufacturer Part Number: ADT7475
• Description: Dbcool Remote Thermal Monitor And Fan Controller
• Manufacturer: Analog Devices, Inc.

ADT7475
Generating SMBALERT Interrupts from THERM Timer
Events
The ADT7475 can generate SMBALERT s when a programma-
ble THERM timer limit has been exceeded. This allows the
system designer to ignore brief, infrequent THERM assertions,
while capturing longer THERM timer events. Register 0x7A is
the THERM timer limit register. This 8-bit register allows a
limit from 0 seconds (first THERM assertion) to 5.825 seconds
to be set before an SMBALERT is generated. The THERM timer
value is compared with the contents of the THERM timer limit
register.
(REGISTER 0x7A)
TIMER LIMIT
THERM
728.32ms
364.16ms
182.08ms
91.04ms
45.52ms
22.76ms
2.914s
1.457s
Figure 29. Functional Block Diagram of ADT7475’s THERM Monitoring Circuitry
0
1
2
3
4
5
6
7
COMPARATOR
Rev. B | Page 24 of 68
CLEARED
ON READ
7 6 5 4 3 2 1 0
IN
If the THERM timer value exceeds the THERM timer limit
value, then the F4P bit (Bit 5) of Interrupt Status Register 2 is
set, and an SMBALERT is generated. Note that the F4P bit (Bit
5) of Interrupt Mask Register 2 (0x75) masks out SMBALERT s
if this bit is set to 1, although the F4P bit of Interrupt Status
Register 2 is still set if the THERM timer limit is exceeded.
Figure 29 is a functional block diagram of the THERM timer,
limit, and associated circuitry. Writing a value of 0x00 to the
THERM timer limit register (0x7A) causes SMBALERT to be
generated on the first THERM assertion. A THERM timer limit
value of 0x01 generates an SMBALERT once cumulative THERM
assertions exceed 45.52 ms.
LATCH
RESET
INTERRUPT MASK REGISTER 2
OUT
1 = MASK
F4P BIT (BIT 5)
INTERRUPT STATUS
REGISTER 2
(REGISTER 0x75)
F4P BIT (BIT 5)
THERM TIMER CLEARED ON READ
2.914s
1.457s
728.32ms
182.08ms
364.16ms
91.04ms
45.52ms
22.76ms
(REGISTER 0x79)
THERM TIMER
SMBALERT
THERM