MPC8248 Freescale Semiconductor, Inc, MPC8248 Datasheet - Page 22
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MPC8248
Manufacturer Part Number
MPC8248
Description
Mpc8248 Powerquicc Ii Integrated Communications Processor
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MPC8248.pdf
(60 pages)
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AC Electrical Characteristics
Figure 10
22
shows signal behavior in MEMC mode.
Generally, all MPC8272 bus and system output signals are driven from the
rising edge of the input clock (CLKin). Memory controller signals,
however, trigger on four points within a CLKin cycle. Each cycle is divided
by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising
edge, and T3 at the falling edge, of CLKin. However, the spacing of T2 and
T4 depends on the PLL clock ratio selected, as shown in
Figure 11
Memory controller signals
CLKin
CLKin
CLKin
1:2, 1:3, 1:4, 1:5, 1:6
PLL Clock Ratio
Figure 11. Internal Tick Spacing for Memory Controller Signals
MPC8272 PowerQUICC II™ Family Hardware Specifications, Rev. 1.5
1:2.5
1:3.5
T1
T1
T1
is a representation of the information in
Table 13. Tick Spacing for Memory Controller Signals
CLKin
V_CLK
T2
T2
T2
Figure 10. MEMC Mode Diagram
T3
T3
T3
1/4 CLKin
3/10 CLKin
4/14 CLKin
NOTE
Tick Spacing (T1 Occurs at the Rising Edge of CLKin)
T4
T4
T4
T2
sp34/sp30
Table
1/2 CLKin
1/2 CLKin
1/2 CLKin
for 1:2, 1:3, 1:4, 1:5, 1:6
for 1:2.5
for 1:3.5
13.
Table
T3
13.
Freescale Semiconductor
3/4 CLKin
8/10 CLKin
11/14 CLKin
T4