MPC905 Integrated Device Technology, MPC905 Datasheet - Page 5

• Manufacturer Part Number: MPC905
• Description: Pci Clock Xtal/lvcmos-input Lvcmos-output 100-mhz 1 6 Clock Generator/fanout Buffer
• Manufacturer: Integrated Device Technology

IDT™ / ICS™ PCI CLOCK GENERATOR/FANOUT BUFFER
MPC905
1:6 PCI CLOCK GENERATOR/FANOUT BUFFR
DRIVING TRANSMISSION LINES
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of approximately 10Ω
the drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to application note AN1091 in the
Timing Solutions data book (DL207/D).
distribution of signals is the method of choice. In a point-to-
point scheme either series terminated or parallel terminated
transmission lines can be used. The parallel technique
terminates the signal at the end of the line with a 50Ω
resistance to V
of DC current and thus only a single terminated line can be
driven by each output of the MPC905 clock driver. For the
series terminated case however there is no DC current draw,
thus the outputs can drive multiple series terminated lines.
Figure 6
terminated line vs two series terminated lines in parallel.
When taken to its extreme the fanout of the MPC905 clock
driver is effectively doubled due to its capability to drive
multiple lines.
results of an output driving a single line vs two lines. In both
cases the drive capability of the MPC905 output buffers is
more than sufficient to drive 50Ω transmission lines on the
incident edge.
delta of only 43 ps exists between the two differently loaded
outputs. The output waveform in
waveform, this step is caused by the impedance mismatch
The MPC905 clock driver was designed to drive high
In most high performance clock networks point-to-point
The waveform plots of
Note from the delay measurements in the simulations a
IN
IN
Figure 6. Single versus Dual Transmission Lines
illustrates an output driving a single series
OUTPUT
OUTPUT
BUFFER
BUFFER
MPC905
MPC905
10Ω
10Ω
CC
/2. This technique draws a fairly high level
R
R
R
Figure 7
S
S
S
= 40Ω
= 40Ω
= 40Ω
Figure 7
show the simulation
Z
Z
Z
O
O
O
= 50Ω
= 50Ω
= 50Ω
shows a step in the
APPLICATIONS INFORMATION
OutA
OutB0
OutB1
5
seen looking into the driver. The parallel combination of the
40Ω series resistor plus the output impedance does not
match the parallel combination of the line impedances. The
voltage wave launched down the two lines will equal:
unity reflection coefficient, to 2.73 V. It will then increment
towards the quiescent 3.0 V in steps separated by one round
trip delay (in this case 4.0 ns).
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the
situation in
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance the line
impedance is perfectly matched.
VL = VS (Zo / Rs + Ro + Zo) = 3.0 (25/55) = 1.36 V
At the load end the voltage will double, due to the near
Since this step is well above the threshold region it will not
3.0
2.5
2.0
1.5
1.0
0.5
0
Figure 8. Optimized Dual Line Termination
Figure 7. Single versus Dual Waveforms
Figure 8
OUTPUT
BUFFER
MPC905
10Ω
t
2
D
IN
= 3.8956
OutA
10Ω + 30Ω || 30Ω = 50Ω ||50Ω
should be used. In this case the series
4
R
R
25Ω = 25Ω
t
6
S
S
D
= 30Ω
= 30Ω
= 3.9386
OutB
TIME (ns)
8
MPC905 REV 4 JANUARY 8, 2008
Z
Z
O
O
= 50Ω
= 50Ω
10
12
14