PIC16C621A Microchip Technology Inc., PIC16C621A Datasheet - Page 58

• Manufacturer Part Number: PIC16C621A
• Description: Eprom-based 8-bit Cmos Microcontrollers
• Manufacturer: Microchip Technology Inc.

PIC16C62X
9.5.1
External interrupt on RB0/INT pin is edge triggered,
either rising if INTEDG bit (OPTION<6>) is set, or fall-
ing, if INTEDG bit is clear. When a valid edge appears
on the RB0/INT pin, the INTF bit (INTCON<1>) is set.
This interrupt can be disabled by clearing the INTE
control bit (INTCON<4>). The INTF bit must be cleared
in software in the interrupt service routine before re-
enabling this interrupt. The RB0/INT interrupt can
wake-up the processor from SLEEP, if the INTE bit was
set prior to going into SLEEP. The status of the GIE bit
decides whether or not the processor branches to the
interrupt vector following wake-up. See Section 9.8 for
details on SLEEP and Figure 9-18 for timing of wake-
up from SLEEP through RB0/INT interrupt.
FIGURE 9-16:
DS30235J-page 56
INSTRUCTION FLOW
GIE bit
(INTCON<7>)
INTF flag
(INTCON<1>)
CLKOUT
INT pin
OSC1
Instruction
executed
Instruction
fetched
Note 1: INTF flag is sampled here (every Q1).
PC
2: Asynchronous interrupt latency = 3-4 T
3: CLKOUT is available only in RC Oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
RB0/INT INTERRUPT
3
Latency is the same whether Inst (PC) is a single cycle or a two-cycle instruction.
Q1
Inst (PC-1)
Inst (PC)
INT PIN INTERRUPT TIMING
1
Q2
PC
Q3
4
Q4
5
Q1
Inst (PC+1)
Inst (PC)
Q2
1
PC+1
Q3
CY
. Synchronous latency = 3 T
Q4
Interrupt Latency
Q1
Dummy Cycle
Q2
9.5.2
An overflow (FFh → 00h) in the TMR0 register will
set the T0IF (INTCON<2>) bit. The interrupt can
be
(INTCON<5>) bit. For operation of the Timer0 module,
see Section 6.0.
9.5.3
An input change on PORTB <7:4> sets the RBIF
(INTCON<0>) bit. The interrupt can be enabled/dis-
abled by setting/clearing the RBIE (INTCON<4>) bit.
For operation of PORTB (Section 5.2).
9.5.4
See Section 7.6 for complete description of comparator
interrupts.
PC+1
—
Note:
Q3
enabled/disabled
Q4
2
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF
interrupt flag may not get set.
TMR0 INTERRUPT
PORTB INTERRUPT
COMPARATOR INTERRUPT
CY
Q1
Dummy Cycle
, where T
Inst (0004h)
Q2
0004h
Q3
 2003 Microchip Technology Inc.
CY
by
= instruction cycle time.
Q4
setting/clearing
Q1
Inst (0005h)
Q2
Inst (0004h)
0005h
Q3
Q4
T0IE