PIC16C774 Microchip Technology Inc., PIC16C774 Datasheet - Page 14
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PIC16C774
Manufacturer Part Number
PIC16C774
Description
28/40-pin, 8-bit Cmos Microcontrollers W/ 12-bit A/d
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16C774.pdf
(201 pages)
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PIC16C77X
TABLE 2-1
DS30275A-page 14
Legend:
Note 1:
Address Name
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Ah
9Eh
9Fh
Bank 1
(4)
(4)
(4)
(4)
(5)
(5)
(1,4)
(4)
2:
3:
4:
5:
OPTION_REG
INDF
PCL
STATUS
FSR
TRISA
TRISB
TRISC
TRISD
TRISE
PCLATH
INTCON
PIE1
PIE2
PCON
SSPCON2
PR2
SSPADD
SSPSTAT
TXSTA
SPBRG
REFCON
LVDCON
ADRESL
ADCON1
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents are transferred to
the upper byte of the program counter.
Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
Bits PSPIE and PSPIF are reserved on the 28-pin devices, always maintain these bits clear.
These registers can be addressed from any bank.
These registers/bits are not implemented on the 28-pin devices read as '0'.
—
—
—
—
—
—
—
PIC16C77X SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter’s (PC) Least Significant Byte
Indirect data memory address pointer
PORTB Data Direction Register
PORTC Data Direction Register
PORTD Data Direction Register
Unimplemented
Unimplemented
Timer2 Period Register
Synchronous Serial Port (I
Unimplemented
Unimplemented
Unimplemented
Baud Rate Generator Register
Unimplemented
Unimplemented
A/D Low Byte Result Register
PSPIE
VRHEN
LVDIE
GCEN
CSRC
ADFM
RBPU
Bit 7
SMP
IRP
GIE
IBF
—
—
—
—
(3)
INTEDG
AKSTAT
VRLEN
VCFG2
PEIE
ADIE
Bit 6
OBF
CKE
RP1
TX9
—
—
—
—
—
bit5
VRHOEN
2
VCFG1
C mode) Address Register
AKDT
TXEN
BGST
T0CS
IBOV
RCIE
Bit 5
T0IE
RP0
(5)
D/A
Advance Information
—
—
—
PORTA Data Direction Register
Write Buffer for the upper 5 bits of the Program Counter
PSPMODE
VRLOEN
LVDEN
VCFG0
SYNC
AKEN
T0SE
INTE
TXIE
Bit 4
TO
—
—
P
PCFG3
SSPIE
BCLIE
RCEN
RBIE
Bit 3
PSA
LV3
PD
—
—
—
—
S
PORTE Data Direction Bits
CCP1IE
PCFG2
BRGH
Bit 2
PS2
T0IF
PEN
R/W
LV2
—
—
—
Z
TMR2IE
PCFG1
RSEN
TRMT
INTF
Bit 1
POR
PS1
LV1
DC
UA
—
—
1999 Microchip Technology Inc.
TMR1IE
CCP2IE
PCFG0
TX9D
RBIF
Bit 0
BOR
SEN
PS0
LV0
BF
—
C
Value on:
0000 0000
0000 0000
0001 1xxx
xxxx xxxx
0000 000x
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
0000 0000
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
0000 -010
0000 -111
--00 0101
--11 1111
---0 0000
0000 ----
0--- 0--0
---- --qq
POR,
BOR
—
—
—
—
—
—
—
other resets
Value on all
0000 0000
0000 0000
000q quuu
uuuu uuuu
0000 000u
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 -010
1111 1111
1111 1111
1111 1111
1111 1111
0000 -111
1111 1111
--00 0101
--11 1111
---0 0000
0000 ----
0--- 0--0
---- --uu
(2)
—
—
—
—
—
—
—