70T3799M Integrated Device Technology, 70T3799M Datasheet

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70T3799M

Manufacturer Part Number
70T3799M
Description
128k X 72 Sync, 3.3v/2.5v Dual-port
Manufacturer
Integrated Device Technology
Datasheet
Features:
Functional Block Diagram
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx
©2005 Integrated Device Technology, Inc.
NOTES:
1. Address A
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed data access
– Commercial: 3.6ns (166MHz)/
– Industrial: 4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Interrupt and Collision Detection Flags
Full synchronous operation on both ports
– 6ns cycle time, 166MHz operation (23.9Gbps bandwidth)
– Fast 3.6ns clock to data out
– Self-timed write allows fast cycle time
and the sleep mode pins themselves (ZZx) are not affected during sleep mode.
FT/PIPE
FT/PIPE
CE
CE
R/W
OE
0L
1L
L
L
L
L
BE
BE
7L
0L
17
is a NC for the IDT70T3799.
4.2ns (133MHz)(max.)
1/0
1/0
1
0
0a 1a
a
CLK
L
I/O
REPEAT
CNTEN
0L
A
ADS
- I/O
17L
A
(1)
0L
L
71L
L
L
COL
INT
Byte 0
0/1
L
L
0h 1h
h
1h 0h
a
HIGH-SPEED 2.5V
256/128K x 72
SYNCHRONOUS
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Counter/
Address
h
CE
CE
Reg.
0
1
1a 0a
L
L
Byte 7
R/W
L
ZZ
L
(2)
D
D
D
D
D
D
D
D
D
ADDR_L
OUT
O UT
OUT
OUT
OUT
OUT
OUT
OUT
IN
_L
B
W
0
L
0-8_L
9-17_L
18-26_L
27-35_L
36-44_L
45-53_L
54-62_L
63-72_L
256/128K x 72
INTERRUPT
DETECTION
MEMORY
COLLISION
ARRAY
CONTROL
LOGIC
1
W
LOGIC
B
7
L
ZZ
D
D
D
D
D
D
D
D
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
ADDR_R
W
B
7
R
0-8_R
9-17_R
18-26_R
27-35_R
36-44_R
45-53_R
54-62_R
63-72_R
D
IN
– 1.7ns setup to clock and 0.5ns hold on all control, data, and
– Data input, address, byte enable and control registers
Separate byte controls for multiplexed bus and bus
matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output Mode
2.5V (±100mV) power supply for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
Industrial temperature range (-40°C to +85°C) is
available at 133MHz
Available in a 324-pin Green Ball Grid Array (BGA)
Includes JTAG Functionality
_R
W
B
R
0
address inputs @ 166MHz
ZZ
R
(2)
Byte 7
R/W
Counter/
Address
0a 1a
R
Reg.
CE
CE
0
1
h
R
R
a
0h 1h
1h 0h
h
Byte 0
COL
0/1
INT
I/O
REPEAT
ADS
CNTEN
R
R
0R
A
A
17R
R
IDT70T3719/99M
- I/O
0
R
(1)
R
R
71R
CLK
TDO
TDI
R
1a 0a
a
1/0
1/0
0
1
,
JUNE 2005
JTAG
5687 drw 01
BE
BE
7R
0R
DSC 5687/1
FT/PIPE
R/W
FT/PIPE
TMS
TRST
TCK
OE
CE
CE
R
R
0R
1R
R
R
,

Related parts for 70T3799M

70T3799M Summary of contents

Page 1

... The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode. ©2005 Integrated Device Technology, Inc. HIGH-SPEED 2.5V 256/128K x 72 ...

Page 2

IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM Description: The IDT70T3719/99M is a high-speed 256K/128K x 72 bit synchro- nous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ...

Page 3

IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM Pin Configuration (2,3,4, ...

Page 4

... DDQX (2.5V), then that port's I/Os and controls will operate at 3.3V DD must be supplied at 3.3V. If OPT is set asserted, the counter will reset to the last valid address loaded for the IDT70T3799M. (0V), then that must be DDQX , i.e., the IH ...

Page 5

IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM Truth Table I—Read/Write and Enable Control OE CE CLK CE Byte Enables 1 0 All All All BE ...

Page 6

IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM Recommended Operating Temperature and Supply Voltage Commercial Industrial NOTES: 1. This is the parameter TA. This is the "instant on" case temperature. Recommended DC Operating Conditions with V NOTES: 1. ...

Page 7

IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM Absolute Maximum Ratings Symbol Rating V V Terminal Voltage TERM with Respect to GND DD ( Terminal Voltage TERM DDQ (V ) with Respect to ...

Page 8

IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter CE I Dynamic Operating DD L Current (Both Outputs Disabled, Ports Active MAX CE ...

Page 9

IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM AC Test Conditions (V Input Pulse Levels (Address & Controls) Input Pulse Levels (I/Os) Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load DATA OUT ∆ tCD ...

Page 10

IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing) Symbol t Clock Cycle Time (Flow-Through) CYC1 (1) t Clock Cycle Time (Pipelined) CYC2 t Clock High ...

Page 11

IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM Timing Waveform of Read Cycle for Pipelined Operation (1,2) (FT/PIPE = CYC2 t CH2 CLK ...

Page 12

IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM Timing Waveform of a Multi-Device Pipelined Read t CYC2 t t CH2 CL2 CLK ADDRESS 0 (B1 0(B1) DATA OUT(B1) ...

Page 13

IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM Timing Waveform of Left Port Write to Pipelined Right Port Read CLK "A" R/W "A " ADDRESS "A" MATCH ...

Page 14

IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM Timing Waveform of Pipelined Read-to-Write-to-Read (2) ( CYC2 t t CH2 CLK ...

Page 15

IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM Timing Waveform of Flow-Through Read-to-Write-to-Read ( CYC1 t t CH1 CL1 CLK BEn W R/ ...

Page 16

IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM Timing Waveform of Pipelined Read with Address Counter Advance t CYC2 t t CH2 CLK ADDRESS t t SAD HAD ADS CNTEN ( ...

Page 17

IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM Timing Waveform of Write with Address Counter Advance (Flow-through or Pipelined Inputs) t CYC2 t CH2 CLK ADDRESS (3) INTERNAL An ADDRESS t t SAD ...

Page 18

IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM Waveform of Interrupt Timing CLK R ADDRESS (3) L 3FFFF ( INS INT ...

Page 19

IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM Waveform of Collision Timing Both Ports Writing with Left Port Clock Leading CLK L t OFS ( ADDRESS L COL L CLK R t ...

Page 20

IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM Timing Waveform - Entering Sleep Mode R/W Timing Waveform - Exiting Sleep Mode R/W OE DATA OUT (4) NOTES IH. 2. All timing is same ...

Page 21

... R or 1FFFE for IDT70T3799M). The message (72 bits) at 3FFFE or 3FFFF (1FFFF or 1FFFE for 70T3799M) is user-defined since addres- sable SRAM location. If the interrupt function is not used, address locations 3FFFE and 3FFFF (1FFFF or 1FFFE for IDT70T3799M) are not used as mail boxes, but as part of the random access memory ...

Page 22

IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM Depth and Width Expansion The IDT70T3719/99M features dual chip enables (refer to Truth Table I) in order to facilitate rapid and simple depth expansion with no requirements for external logic. ...

Page 23

IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM JTAG Timing Specifications t JF TCK (1) Device Inputs / TDI/TMS (2) Device Outputs / TDO TRST t JRST NOTES: 1. Device inputs = All device inputs except TDI, TMS, ...

Page 24

... Array B Revision Number (31:28) 0x0 (1) 0x330 IDT Device ID (27:12) IDT JEDEC ID (11:1) 0x33 ID Register Indicator Bit (Bit 0) NOTE: 1. Device ID for IDT70T3719M is 0x330. Device ID for IDT70T3799M is 0x331. Scan Register Sizes Register Name Instruction (IR) Bypass (BYR) Identification (IDR) Boundary Scan (BSR) System Interface Parameters Instruction EXTEST ...

Page 25

... I G Green 324-pin BGA (BBG-324) BB 166 Commercial Only 133 Commercial & Industrial Standard Power S 70T3719M 18Mbit (256K x 72) 2.5V Synchronous Dual-Port RAM 70T3799M 9Mbit (128K x 72) 2.5V Synchronous Dual-Port RAM Clock Specifications Input Duty Input Maximum Cycle Capacitance Frequency Requirement 15pF 40% 166 for SALES: ...

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