STI5202 STMicroelectronics, STI5202 Datasheet - Page 4
STI5202
Manufacturer Part Number
STI5202
Description
Low-cost Set-top Box Decoder For H.264 And Microsoft Vc1
Manufacturer
STMicroelectronics
Datasheet
1.STI5202.pdf
(9 pages)
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Typical applications
1.1
4/9
Detailed features
The STi5202 is a single-chip,standard-definition video decoder including:
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The STi5202 also features the following embedded interfaces:
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The processor subsystem uses the ST40 32-bit superscaler RISC CPU and includes:
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The transport subsystem includes:
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Flexible audio decoder
Windows Media
Microsoft
Linux
Transport filtering and descrambling
SVP compliant
Graphics engine and dual display: standard and enhanced definition
USB 2.0 host controller/PHY interface
DVI/HDMI™ output (optional)
Low-cost modem
100BT ethernet controller with integrated MAC and MII/RMII interface for external PHY
266 MHz, 2-way set associative 16-Kbyte ICache, 32-Kbyte DCache, MMU
5-stage pipeline, delayed branch support
Floating point unit, matrix operation support
Debug port, interrupt controller
TS merger/router
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Programmable transport interfaces (PTIs)
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Merging of 3 external transport streams (2 serial/parallel inputs, 1 bidirectional
interface)
Transport streams from memory support
NRSS-A module interface
Two programmable transport interfaces
Two transport stream demultiplexers: DVB, DIRECTV®, ATSC, ARIB, OpenCable,
DCII
Integrated DES, AES, DVB and Multi2 descramblers
NDS random access scrambled stream protocol (RASP) compliant
NDS ICAM CA
Support for VGS, Passage
®
, Windows
®
VC-1, WMA9 and H.264 MPEG2 support
™
®
DRM support
CE and OS21 compatible ST40 CPU core: 266 MHz
STi5202