U6808B ATMEL Corporation, U6808B Datasheet - Page 5
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U6808B
Manufacturer Part Number
U6808B
Description
Special Fail-safe Ic
Manufacturer
ATMEL Corporation
Datasheet
1.U6808B.pdf
(14 pages)
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Part Number:
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5.5
5.6
5.7
5.8
4707B–AUTO–10/05
RESET Input
WD-OK Output
Watchdog State Diagram
Explanation
During power-on and under/overvoltage detection a reset signal is fed to this pin. It resets the
watchdog timer and sets the initial state.
After the up/down counter is incremented to status 3 (see
the WD-OK output becomes logic 1. This information is available for the microcontroller at the
open-collector output ENABLE. If on the other hand the up/down counter is decremented to 0
the RS flip-flop is reset, the WD-OK output and the ENABLE output are disabled. The WD-OK
output also controls a dual MUX stage which shifts the time window by one clock after a suc-
cessful trigger, thus forming a hysteresis to provide stable conditions for the evaluation of the
trigger signal good or false. The WD-OK signal is also reset in case the watchdog counter is not
reset after 250 clocks (missing trigger signal).
Figure 5-2.
In each block, the first character represents the state of the counter. The second notation indi-
cates the fault status of the counter. A fault status is indicated by an F and a no fault status is
indicated by an NF. When the watchdog is powered up initially, the counter starts out at the 0/F
block (initial state). Good indicates that a pulse has been received whose width resides within
the timing window. Bad indicates that a pulse has been received whose width is either too short
or too long.
Watchdog State Diagram
Initial status
bad
good
O/F
bad
bad
1/NF
1/F
good
good
bad
bad
2/NF
2/F
bad
Figure
good
good
3/NF
5-2) the RS flip-flop is set and
good
U6808B
5