U6813B ATMEL Corporation, U6813B Datasheet - Page 5

• Manufacturer Part Number: U6813B
• Description: U6813b Fail-safe Ic With High-side And Relay Driver
• Manufacturer: ATMEL Corporation

4.1
4.2
4.3
4.4
4.5
Figure 4-2.
4543B–AUTO–10/05
Update rate is
Time/s
too fast
WDI Input (Pin 11)
WDC Input (Pin 10)
OSCERR Input
RESET Input
WD-OK Output
79/ f
Watchdog Timing Diagram with Tolerances
WDC
either too fast or
Update rate is
good
The microcontroller has to provide a trigger signal with the frequency f
input. A positive edge of f
the up/down counter.The latter one counts only from 0 to 3 or reverse. Each correct trigger
increments the up/down counter by 1, each wrong trigger decrements it by 1. As soon as the
counter reaches status 3, the RS flip-flop is set; see
missing incoming trigger signal is detected after 250 clocks of the internal watchdog frequency
f
It is to be equiped by external R/C components. By means of an external R/C circuitry, the IC
generates a time base (frequency f
time window refers to a frequency of f
A smart watchdog has to ensure that internal problems with its own time base are detected and
do not lead to an undesired status of the complete system. If the RC oscillator stops oscillating,
a signal is fed to the OSCERR input after a time-out delay. It resets the up/down counter and
disables the WD-OK output. Without this reset function, the watchdog would freeze its current
status when f
During power-on and under/overvoltage detection, a reset signal is fed to this pin. It resets the
watchdog timer and sets the initial state.
After the up/down counter has reached to status 3 (see
the RS flip-flop is set and the WD-OK output becomes logic “1”. As WD-OK is directly connected
to the enable pins, the open-collector output P-EN provides also logic “1” while a logic “0” is
available at N-EN output. If on the other hand the up/down counter is decremented to “0”, the RS
flip-flop is reset, the WD-OK output and the P-EN output are logic “0” and N-EN output is logic
“1”. The WD-OK output also controls a dual MUX stage which shifts the time window by one
clock after a successful trigger, thus forming a hysteresis to provide stable conditions for the
evaluation of the trigger signal “good or false”. The WD-OK signal is also reset in case the
watchdog counter is not reset after 250 clocks (missing trigger signal).
RC
80/ f
(see WD_OK output) and resets the up/down counter directly.
WDC
update rate is good
Watchdog Window
RC
stops.
169/ f
WDI
detected by a slope detector resets the binary counter and clocks
WDC
either too slow
Update rate is
or good
WDC
WDC
) independent from the microcontroller. The watchdog’s
= 100
170/ f
WDC
Update rate is
too slow
f
WDI
.
Figure 4-3
Figure
250/ f
4-3, Watchdog State Diagram),
WDC
(Watchdog state diagram). A
either too slow
Update rate is
or pulse has
dropped out
WDI
which is fed to the WDI
U6813B
251/ f
dropped out
Pulse has
WDC
5