NCP1271 ON Semiconductor, NCP1271 Datasheet - Page 13

• Manufacturer Part Number: NCP1271
• Description: Soft?skip? Mode Standby Pwm Controller With Adjustable Skip Level And External Latch
• Manufacturer: ON Semiconductor

Ramp Compensation
subharmonic oscillations. These oscillations take place at
half the switching frequency and occur only during
continuous conduction mode (CCM) with a duty-cycle
greater than 50%. To lower the current loop gain, one
usually injects between 50 and 75% of the inductor down
slope. The NCP1271 generates an internal current ramp
that is synchronized with the clock. This current ramp is
then routed to the CS pin. Figures 32 and 33 depict how the
ramp is generated and utilized. Ramp compensation is
simply formed by placing a resistor, R
pin and the sense resistor.
100 mA. Over a 65 kHz frequency with an 80% max duty
cycle, that corresponds to an 8.1 mA/ms ramp. For a typical
flyback design, let's assume that the primary inductance
(Lp) is 350 mH, the SMPS output is 19 V, the Vf of the
output diode is 1 V and the Np:Ns ratio is 10:1. The OFF
time primary current slope is given by:
this becomes or 57 mV/ms. If we select 75% of the
downslope as the required amount of ramp compensation,
then we shall inject 43 mV/ms. Therefore, R
equal to:
Current Sense Information brings Ramp Compensation
Ramp compensation is a known mean to cure
For the NCP1271, the current ramp features a swing of
When projected over an Rsense of 0.1 W (for example),
100uA
Oscillator
Figure 33. Inserting a Resistor in Series with the
Current
Ramp
Clock
(Vout ) Vf) @
Figure 32. Internal Ramp Current Source
0
Lp
Ramp current, I
Np
Ns
+ 571 V mH + 571 mA ms
100 mA Peak
ramp
DRIVE
CS
80% of period
ramp
100% of period
, between the CS
time
ramp
R
R
ramp
sense
is simply
http://onsemi.com
(eq. 3)
NCP1271
13
less then 10 kW. Values larger than this will begin to limit
the effective duty cycle of the controller and may result in
reduced transient response.
Frequency Jittering
signature by spreading the energy in the vicinity of the main
switching component. The NCP1271 switching frequency
ranges from +7.5% to -7.5% of the switching frequency in
a linear ramp with a typical period of 6 ms. Figure 34
demonstrates how the oscillation frequency changes.
Fault Detection
circuitry. When an overload (or short circuit) event occurs,
the output voltage collapses and the optocoupler does not
conduct current. This opens the FB pin (pin 2) and V
internally pulled higher than 3.0 V. Since (V
than 1 V, the controller activates an error flag and starts a
130 ms timer. If the output recovers during this time, the
timer is reset and the device continues to operate normally.
However, if the fault lasts for more than 130 ms, then the
driver turns off and the device enters the V
Hiccup mode discussed earlier. At the end of the double
hiccup, the controller tries to restart the application.
FB
It is recommended that the value of R
Frequency jittering is a method used to soften the EMI
Figure 35 details the timer-based fault detection
(The values are for the 100 kHz frequency option)
Figure 35. Block Diagram of Timer-Based Fault
2
V FB
Oscillator Frequency
4.8V
Figure 34. Frequency Jittering
R ramp +
V SS
Softstart
1V max
V FB
3
+
-
6 ms
43 mV ms
8.1 mA ms
Detection
130ms
delay
+ 5.3 kW
ramp
&
FB
100 kHz
107.5 kHz
be limited to
92.5 kHz
time
/3) is greater
CC
disable Drv
Fault
Double
(eq. 4)
FB
is