MC56F8035 Freescale Semiconductor, Inc, MC56F8035 Datasheet
MC56F8035
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MC56F8035 Summary of contents
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Data Sheet Technical Data 56F8000 16-bit Digital Signal Controllers MC56F8025 Rev. 6 02/2010 freescale.com ...
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Version History Rev. 0 Initial public release. Rev. 1 • In Table 5-3, changed the ITCN_BASE address from $00 F060 (incorrect value) to $00 F0E0 (the correct value). • In Table 10-4, added an entry for flash data retention with ...
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... Input Voltage High XTAL not driven by an external clock XTAL driven by an external clock source“ Changed COUTB_A to CMPBO throughout Added MC56F8035 device Added MC56F8025MLD to the orderable parts In the System Integration Module (SIM) chapter, fixed typos Added IPS0_PSRC2 field to SIM_IPS0 register Please see http://www ...
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General Description • MIPS at 32MHz core frequency • DSP and MCU functionality in a unified, C-efficient architecture • 56F8035 offers 64KB (32K x 16) Program Flash • 56F8025 offers 32KB (16K x 16) Program Flash ...
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Data Sheet Table of Contents Part 1 Overview 1.1 56F8035/56F8025 Features . . . . ...
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Part 1 Overview 1.1 56F8035/56F8025 Features 1.1.1 Digital Signal Controller Core • Efficient 16-bit 56800E family Digital Signal Controller (DSC) engine with dual Harvard architecture • As many as 32 Million Instructions Per Second (MIPS) at 32MHz core frequency • ...
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Peripheral Circuits for 56F8035/56F8025 • One multi-function six-output Pulse Width Modulator (PWM) module — 96MHz PWM operating clock — 15 bits of resolution — Center-aligned and edge-aligned PWM signal mode — Four programmable fault inputs with programmable ...
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Full-duplex operation — Master and slave modes — Four-words-deep FIFOs available on both transmitter and receiver — Programmable Length Transactions ( bits) • One Inter-Integrated Circuit (I — Operates up to 400kbps — Supports both master and ...
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The 56800E core is based on a dual Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style ...
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The PWM_reload_sync output can be connected to the Timer’s Channel 3 input and the Timer’s Channels 2 and 3 outputs are connected to the ADC sync inputs. Timer Channel 3 output is connected to SYNC0 and Timer Channel ...
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To/From IPBus Bridge OCCS (ROSC / PLL / OSC) GPIO A GPIO B GPIO C GPIO D Freescale Semiconductor Interrupt Controller Low-Voltage Interrupt POR & LVI System POR SIM COP Reset COP IPBus (Continues on Figure 1-3) Figure 1-2 Peripheral ...
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To/From IPBus Bridge IPBus INTC PIT0 MSTR_CNT_EN MSTR_CNT_EN PIT1 MSTR_CNT_EN PIT2 2 3 Sync0, Over/Under Sync1 Limits ADC Figure 1-3 56F8035/56F8025 I/O Pin-Out Muxing (Part 1/5) 12 SYNC 3 SYNC SYNC SYNC0, SYNC1 on Figure 1-7 LIMIT on Figure 1-6 ...
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To/From IPBus Bridge QSCI0 QSPI0 IPBus Figure 1-4 56F8035/56F8025 I/O Pin-Out Muxing (Part 2/5) Freescale Semiconductor RXD0, TXD0 2 TA2, TA3 on Figure 1-7 MISO0, MOSI0 2 SCLK0, SS0 2 2 SCL, SDA 2 2 56F8035/56F8025 Data ...
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To/From IPBus Bridge CMP_IN1 CMP_IN3 CMPA CMP_OUT CMP_IN2 Export Import DAC0 DAC1 Import Export CMP_IN2 CMP_OUT CMPB CMP_IN3 CMP_IN1 IPBus Figure 1-5 56F8035/56F8025 I/O Pin-Out Muxing (Part 3/5) 14 FAULT1 on Figure 1-6 TA2 on Figure 1-7 CMPAI1 CMPAI3 CMPAO ...
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To/From IPBus Bridge PWM RELOAD PSRC0 - 1 TA1 on IPBus Figure 1-6 56F8035/56F8025 I/O Pin-Out Muxing (Part 4/5) Freescale Semiconductor TA0 on Figure 1-7 2 TA2 - 3 on Figure 1-7 4 PWM0 - 3 FAULT0 PWMA4 - 5 ...
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To/From IPBus Bridge T0o T0i T1o T1i TMRA T2o T2i T3o T3i IPBus Figure 1-7 56F8035/56F8025 I/O Pin-Out Muxing (Part 5/5) 16 TA0o on TA0 on TA1 on CMPAO on SYNC1 on TA2o on TA2 on TA2 on TA2 on ...
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... Description Logic State True False True False are defined by individual product specifications. 56F8035/56F8025 Data Sheet, Rev. 6 Product Documentation Order Number DSP56800ERM MC56F80xxRM 56F80xxBLUG MC56F8035/56F8025 MC56F8035/56F8025E Signal State 1 Voltage Asserted Deasserted Asserted ...
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Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56F8035/56F8025 are organized into functional groups, as detailed in Table 2-1. Table 2-2 summarizes all device pins. In signals present on a pin, sorted by pin number. ...
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In Table 2-2, peripheral pins in bold identify reset state. Pin Pin Name Signal Name # 1 GPIOB6 GPIOB6, RXD0, SDA, CLKIN 2 GPIOB1 GPIOB1, SS0, SDA 3 GPIOB7 GPIOB7, TXD0, SCL 4 GPIOB5 GPIOB5, TA1, FAULT3, CLKIN 5 GPIOA9 ...
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Table 2-2 56F8035/56F8025 Pins (Continued) Pin Pin Name Signal Name # 28 VSS_IO VDD_IO GPIOB0 GPIOB0, SCLK0, SCL 31 GPIOA4 GPIOA4, PWM4, TA2, FAULT1 32 GPIOA2 GPIOA2, PWM2 33 GPIOA3 GPIOA3, PWM3 34 VCAP ...
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Power Ground Power Ground Other Supply Ports GPIOD4 (EXTAL) OSC Port or GPIO GPIOD5 (XTAL, CLKIN) RESET RESET (GPIOA7) or GPIOA GPIOB0 (SCLK0, SCL) QSPI GPIOB1 (SS0, SDA PWM GPIOB2 (MISO0, TA2, PSRC0) or TMRA ...
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Signal Pins After reset, each pin is configured for its primary function (listed first). Any alternate functionality must be programmed. Table 2-3 56F8035/56F8025 Signal and Package Information for the 44-Pin LQFP Signal LQFP Type Name Pin No. V ...
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Table 2-3 56F8035/56F8025 Signal and Package Information for the 44-Pin LQFP Signal LQFP Type Name Pin No. GPIOA0 40 Input/ Output (PWM0) Output GPIOA1 39 Input/ Output (PWM1) Output GPIOA2 32 Input/ Output (PWM2) Output GPIOA3 33 Input/ Output (PWM3) ...
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Table 2-3 56F8035/56F8025 Signal and Package Information for the 44-Pin LQFP Signal LQFP Type Name Pin No. GPIOA4 31 Input/ Output (PWM4) Output 1 Input/ (TA2 ) Output 2 (FAULT1 ) Input 1 The TA2 signal is also brought out ...
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Table 2-3 56F8035/56F8025 Signal and Package Information for the 44-Pin LQFP Signal LQFP Type Name Pin No. GPIOA6 24 Input/ Output (FAULT0) Input (TA0) GPIOA8 26 Input/ Output (FAULT1) Input (TA2) Input/ Output (CMPAI1) Input GPIOA9 5 Input/ Output (FAULT2) ...
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Table 2-3 56F8035/56F8025 Signal and Package Information for the 44-Pin LQFP Signal LQFP Type Name Pin No. GPIOA10 25 Input/ Output (CMPAI2) Input GPIOA11 6 Input/ Output (CMPBI2) Input GPIOB0 30 Input/ Output (SCLK0) Input/ Output 5 Input/ (SCL ) ...
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Table 2-3 56F8035/56F8025 Signal and Package Information for the 44-Pin LQFP Signal LQFP Type Name Pin No. GPIOB2 23 Input/ Output (MISO0) Input/ Output 7 Input/ (TA2 ) Output Input (PSRC0) 7 The TA2 signal is also brought out on ...
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Table 2-3 56F8035/56F8025 Signal and Package Information for the 44-Pin LQFP Signal LQFP Type Name Pin No. GPIOB5 4 Input/ Output (TA1) Input/ Output (FAULT3) Input (CLKIN) Input GPIOB6 1 Input/ Output (RXD0) Input 9 Input/ (SDA ) Output Input ...
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Table 2-3 56F8035/56F8025 Signal and Package Information for the 44-Pin LQFP Signal LQFP Type Name Pin No. GPIOB10 20 Input/ Output (CMPAO) Output GPIOB11 42 Input/ Output (CMPBO) Output GPIOC0 16 Input/ Output (ANA0 & Analog CMPAI3) Input GPIOC1 15 ...
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Table 2-3 56F8035/56F8025 Signal and Package Information for the 44-Pin LQFP Signal LQFP Type Name Pin No. GPIOC3 13 Input/ Output (ANA3) Analog Input (V ) Analog REFLA Input GPIOC4 7 Input/ Output (ANB0 & Analog CMPBI3) Input GPIOC5 8 ...
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Table 2-3 56F8035/56F8025 Signal and Package Information for the 44-Pin LQFP Signal LQFP Type Name Pin No. GPIOC7 10 Input/ Output (ANB3) Analog Input (V ) Input REFLB GPIOD4 38 Input/ Output (EXTAL) Analog Input GPIOD5 37 Input/ Output (XTAL) ...
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Table 2-3 56F8035/56F8025 Signal and Package Information for the 44-Pin LQFP Signal LQFP Type Name Pin No. TDO 44 Output (GPIOD1) Input/ Output TCK 19 Input (GPIOD2) Input/ Output TMS 43 Input (GPIOD3) Input/ Output Return to Table 2-2 32 ...
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Part 3 OCCS 3.1 Overview The On-Chip Clock Synthesis (OCCS) module allows designers using an internal relaxation oscillator, an external crystal external clock to run 56F8000 family devices at user-selectable frequencies up to 32MHz. For details, see the ...
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The 56F8000 family devices’ on-chip clock synthesis module has the following registers: • Control Register (OCCS_CTRL) • Divide-by Register (OCCS_DIVBY) • Status Register (OCCS_STAT) • Shutdown Register (OCCS_SHUTDN) • Oscillator Control Register (OCCS_OCTRL) For more information on these registers, please ...
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Crystal Frequency = 4 - 8MHz (optimized for 8MHz) EXTAL XTAL EXTAL XTAL R z CL1 CL2 Figure 3-1 External Crystal Oscillator Circuit 3.6 Ceramic Resonator The internal crystal oscillator circuit is also designed to interface with a ceramic resonator ...
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Figure 3-3 Connecting an External Clock Signal using XTAL 3.8 Alternate External Clock Input The recommended method of connecting an external clock is illustrated in source is connected to GPIO6/RXD (primary) or GPIOB5/TA1/FAULT3/XTAL/EXTAL (secondary). The user has the option of ...
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Table 4-1 Chip Memory Configurations On-Chip Memory Program Flash (PFLASH) Unified RAM (RAM) 4.2 Interrupt Vector Table Table 4-2 provides the 56F8035/56F8025’s reset and interrupt priority structure, including on-chip peripherals. The table is organized with higher-priority vectors at the top ...
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Table 4-2 Interrupt Vector Table Contents Vector Priority Peripheral Number Level 0-2 20-23 GPIOD 24 0-2 GPIOC 25 0-2 GPIOB 26 0-2 GPIOA 27 0-2 QSPI0 28 0-2 QSPI0 29 0-2 30-31 ...
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Program Map The Program Memory map is shown in Table 4-3 Program Memory Map Begin/End Address P: $1F FFFF P: $00 9000 P: $00 8FFF P: $00 8000 P: $00 7FFF P: $00 0000 1. All addresses are 16-bit ...
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Table 4-5 Data Memory Map Begin/End Address X:$00 FFFF X:$00 F000 X:$00 EFFF X:$00 8800 X:$00 87FF X:$00 8000 X:$00 7FFF X:$00 1000 X:$00 0FFF X:$00 0000 1. All addresses are 16-bit Word addresses. 2. This RAM is shared with ...
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Program Reserved RAM Flash Figure 4-1 Dual Port RAM for 56F8035 Program Reserved RAM Flash Reserved Figure 4-2 Dual Port RAM for 56F8025 4.5 EOnCE Memory Map Figure 4-7 lists all EOnCE registers necessary to access or control the EOnCE. ...
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Table 4-7 EOnCE Memory Map (Continued) Address Register Acronym X:$FF FFFB - X:$FF FFA1 X:$FF FFA0 OCR X:$FF FF9F X:$FF FF9E OSCNTR (24 bits) X:$FF FF9D OSR X:$FF FF9C OBASE X:$FF FF9B OTBCR X:$FF FF9A OTBPR X:$FF FF99 X:$FF FF98 ...
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Table 4-8 Data Memory Peripheral Base Address Map Summary (Continued) Peripheral ADC PWM ITCN SIM COP CLK, PLL, OSC Power Supervisor GPIO Port A GPIO Port B GPIO Port C GPIO Port D PIT 0 PIT 1 PIT 2 DAC ...
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Table 4-9 Quad Timer A Registers Address Map (Continued) Register Acronym TMRA0_ENBL TMRA1_COMP1 TMRA1_COMP2 TMRA1_CAPT TMRA1_LOAD TMRA1_HOLD TMRA1_CNTR TMRA1_CTRL TMRA1_SCTRL TMRA1_CMPLD1 TMRA1_CMPLD2 TMRA1_CSCTRL TMRA1_FILT TMRA2_COMP1 TMRA2_COMP2 TMRA2_CAPT TMRA2_LOAD TMRA2_HOLD TMRA2_CNTR TMRA2_CTRL TMRA2_SCTRL TMRA2_CMPLD1 TMRA2_CMPLD2 TMRA2_CSCTRL TMRA2_FILT TMRA3_COMP1 TMRA3_COMP2 TMRA3_CAPT TMRA3_LOAD ...
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Table 4-9 Quad Timer A Registers Address Map (Continued) Register Acronym TMRA3_CSCTRL TMRA3_FILT Table 4-10 Analog-to-Digital Converter Registers Address Map Register Acronym ADC_CTRL1 ADC_CTRL2 ADC_ZXCTRL ADC_CLIST 1 ADC_CLIST 2 ADC_CLIST 3 ADC_CLIST 4 ADC_SDIS ADC_STAT ADC_RDY ADC_LIMSTAT ADC_ZXSTAT ADC_RSLT0 ADC_RSLT1 ...
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Table 4-10 Analog-to-Digital Converter Registers Address Map (Continued) Register Acronym ADC_LOLIM1 ADC_LOLIM2 ADC_LOLIM3 ADC_LOLIM4 ADC_LOLIM5 ADC_LOLIM6 ADC_LOLIM7 ADC_HILIM0 ADC_HILIM1 ADC_HILIM2 ADC_HILIM3 ADC_HILIM4 ADC_HILIM5 ADC_HILIM6 ADC_HILIM7 ADC_OFFST0 ADC_OFFST1 ADC_OFFST2 ADC_OFFST3 ADC_OFFST4 ADC_OFFST5 ADC_OFFST6 ADC_OFFST7 ADC_PWR ADC_CAL Table 4-11 Pulse Width Modulator ...
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Table 4-11 Pulse Width Modulator Registers Address Map (Continued) Register Acronym PWM_VAL1 PWM_VAL2 PWM_VAL3 PWM_VAL4 PWM_VAL5 PWM_DTIM0 PWM_DTIM1 PWM_DMAP1 PWM_DMAP2 PWM_CNFG PWM_CCTRL PWM_PORT PWM_ICCTRL PWM_SCTRL PWM_SYNC PWM_FFILT0 PWM_FFILT1 PWM_FFILT2 PWM_FFILT3 Table 4-12 Interrupt Control Registers Address Map Register Acronym ITCN_IPR0 ...
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Table 4-12 Interrupt Control Registers Address Map (Continued) Register Acronym ITCN_IRQP0 ITCN_IRQP1 ITCN_IRQP2 ITCN_IRQP3 ITCN_ICTRL Table 4-13 SIM Registers Address Map Register Acronym Address Offset SIM_CTRL SIM_RSTAT SIM_SWC0 SIM_SWC1 SIM_SWC2 SIM_SWC3 SIM_MSHID SIM_LSHID SIM_PWR SIM_CLKOUT SIM_PCR SIM_PCE0 SIM_PCE1 SIM_SD0 SIM_SD1 ...
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Table 4-13 SIM Registers Address Map (Continued) Register Acronym Address Offset SIM_IPS2 Table 4-14 Computer Operating Properly Registers Address Map Register Acronym COP_CTRL COP_TOUT COP_CNTR Table 4-15 Clock Generation Module Registers Address Map Register Acronym OCCS_CTRL OCCS_DIVBY OCCS_STAT OCCS_OCTRL OCCS_CLKCHK ...
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Table 4-17 GPIOA Registers Address Map Register Acronym GPIOA_PUPEN GPIOA_DATA GPIOA_DDIR GPIOA_PEREN GPIOA_IASSRT GPIOA_IEN GPIOA_IEPOL GPIOA_IPEND GPIOA_IEDGE GPIOA_PPOUTM GPIOA_RDATA GPIOA_DRIVE Table 4-18 GPIOB Registers Address Map Register Acronym GPIOB_PUPEN GPIOB_DATA GPIOB_DDIR GPIOB_PEREN GPIOB_IASSRT GPIOB_IEN GPIOB_IEPOL GPIOB_IPEND GPIOB_IEDGE GPIOB_PPOUTM GPIOB_RDATA GPIOB_DRIVE ...
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Table 4-19 GPIOC Registers Address Map Register Acronym GPIOC_DATA GPIOC_DDIR GPIOC_PEREN GPIOC_IASSRT GPIOC_IEN GPIOC_IEPOL GPIOC_IPEND GPIOC_IEDGE GPIOC_PPOUTM GPIOC_RDATA GPIOC_DRIVE Freescale Semiconductor (GPIOC_BASE = $00 F170) Address Offset Register Description $1 Data Register $2 Data Direction Register $3 Peripheral Enable Register ...
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Table 4-20 GPIOD Registers Address Map Register Acronym GPIOD_PUPEN GPIOD_DATA GPIOD_DDIR GPIOD_PEREN GPIOD_IASSRT GPIOD_IEN GPIOD_IEPOL GPIOD_IPEND GPIOD_IEDGE GPIOD_PPOUTM GPIOD_RDATA GPIOD_DRIVE Table 4-21 Programmable Interval Timer 0 Registers Address Map Register Acronym PIT0_CTRL PIT0_MOD PIT0_CNTR Table 4-22 Programmable Interval Timer 1 ...
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Table 4-23 Programmable Interval Timer 2 Registers Address Map (Continued) Register Acronym PIT2_MOD PIT2_CNTR Table 4-24 Digital-to-Analog Converter 0 Registers Address Map Register Acronym DAC0_CTRL DAC0_DATA DAC0_STEP DAC0_MINVAL DAC0_MAXVAL Table 4-25 Digital-to-Analog Converter 0 Registers Address Map Register Acronym DAC1_CTRL ...
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Table 4-27 Comparator B Registers Address Map (Continued) Register Acronym CMPB_FILT Table 4-28 Queued Serial Communication Interface 0 Registers Address Map Register Acronym QSCI0_RATE QSCI0_CTRL1 QSCI0_CTRL2 QSCI0_STAT QSCI0_DATA Table 4-29 Queued Serial Peripheral Interface 0 Registers Address Map Register Acronym ...
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Table 4-30 I Register Acronym I2C_RISTAT I2C_RXFT I2C_TXFT I2C_CLRINT I2C_CLRRXUND I2C_CLRRXOVR I2C_CLRTXOVR I2C_CLRRDREQ I2C_CLRTXABRT I2C_CLRRXDONE I2C_CLRACT I2C_CLRSTPDET I2C_CLRSTDET I2C_CLRGC I2C_ENBL I2C_STAT I2C_TXFLR I2C_RXFLR I2C_TXABRTSRC Table 4-31 Flash Module Registers Address Map Register Acronym FM_CLKDIV FM_CNFG FM_SECHI FM_SECLO FM_PROT FM_USTAT FM_CMD ...
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Table 4-31 Flash Module Registers Address Map Register Acronym FM_IFROPT_1 FM_TSTSIG Part 5 Interrupt Controller (ITCN) 5.1 Introduction The Interrupt Controller (ITCN) module arbitrates between various interrupt requests (IRQs), to signals the 56800E core when an interrupt of sufficient priority ...
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I1 bits in its status register. Freescale Semiconductor 56F8035/56F8025 Data Sheet, Rev. 6 Functional Description 57 ...
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Table 5-1 Interrupt Mask Bit Definition SR[9] (I1) SR[8] (I0 The IPIC bits of the ICTRL register reflect the state of the priority level being presented to the 56800E core. Table 5-2 Interrupt Priority Encoding IPIC_VALUE[1:0] ...
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Block Diagram Priority Level 2 -> 4 INT1 Decode Priority Level 2 -> 4 INT64 Decode Figure 5-1 Interrupt Controller Block Diagram 5.5 Operating Modes The ITCN module design contains two major modes of operation: • Functional Mode The ...
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Register Base Address + Acronym IPR0 $0 IPR1 $1 IPR2 $2 IPR3 $3 IPR4 $4 IPR5 $5 IPR6 $6 VBA $7 FIM0 $8 FIVAL0 $9 FIVAH0 $A FIM1 $B FIVAL1 $C FIVAH1 $D IRQP0 $E IRQP1 $F IRQP2 $10 IRQP3 ...
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Add. Register 15 14 Offset Name R $0 IPR0 PLL IPL IPR1 GPIOD IPL W R QSCI0_XMIT $2 IPR2 IPL IPR3 I2C_ERR IPL IPR4 TMRA_3 IPL IPR5 PIT1 ...
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Interrupt Priority Register 0 (IPR0) Base + $ Read PLL IPL Write RESET Figure 5-3 Interrupt Priority Register 0 (IPR0) 5.6.1.1 PLL Loss of Reference or Change in Lock Status Interrupt Priority Level ...
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EOnCE Transmit Register Empty Interrupt Priority Level (TX_REG IPL)— Bits 7–6 This field is used to set the interrupt priority level for the EOnCE Transmit Register Empty IRQ. This IRQ is limited to priorities 1 through ...
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Interrupt Priority Register 1 (IPR1) Base + $ Read 0 GPIOD IPL Write RESET Figure 5-4 Interrupt Priority Register 1 (IPR1) 5.6.2.1 GPIOD Interrupt Priority Level (GPIOD IPL)—Bits 15–14 This field is used ...
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FM Error Interrupt Priority Level (FM_ERR IPL)—Bits 1–0 This field is used to set the interrupt priority level for the FM Error IRQ. This IRQ is limited to priorities 0 through disabled by default. • 00 ...
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QSPI 0 Receiver Full Interrupt Priority Level (QSPI0_RCV IPL)—Bits 7–6 This field is used to set the interrupt priority level for the QSPI0 Receiver Full IRQ. This IRQ is limited to priorities 0 through disabled by ...
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I C Error Interrupt Priority Level (I2C_ERR IPL)—Bits 15–14 This field is used to set the interrupt priority level for the I 0 through disabled by default. • IRQ disabled (default) • 01 ...
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Interrupt Priority Register 4 (IPR4) Base + $ Read TMRA_3 IPL TMRA_2 IPL Write RESET Figure 5-7 Interrupt Priority Register 4 (IPR4) 5.6.5.1 Timer A, Channel 3 Interrupt Priority Level (TMRA_3 IPL)— Bits ...
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Timer A, Channel 0 Interrupt Priority Level (TMRA_0 IPL)— Bits 9–8 This field is used to set the interrupt priority level for the Timer A, Channel 0 IRQ. This IRQ is limited to priorities 0 through ...
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IRQ is priority level 1 • IRQ is priority level 2 5.6.6 Interrupt Priority Register 5 (IPR5) Base + $ Read PIT1 IPL PIT0 IPL Write RESET Figure 5-8 ...
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Comparator A Interrupt Priority Level (COMPA IPL)— Bits 9–8 This field is used to set the interrupt priority level for the Comparator IRQ. This IRQ is limited to priorities 0 through disabled by default. • 00 ...
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ADC Zero Crossing Interrupt Priority Level (ADC_ZC IPL)—Bits 7–6 This field is used to set the interrupt priority level for the ADC Zero Crossing IRQ. This IRQ is limited to priorities 0 through disabled by default. ...
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Vector Base Address Register (VBA) Base + $ Read 0 0 Write 1 RESET The 56F8035 resets to a value 0000. This corresponds to reset addresses ...
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Fast Interrupt 0 Vector Address Low Register (FIVAL0) Base + $ Read Write RESET Figure 5-12 Fast Interrupt 0 Vector Address Low Register (FIVAL0) 5.6.10.1 Fast Interrupt 0 Vector Address Low (FIVAL0)—Bits 15–0 ...
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Interrupt vector is set to any other priority. A Fast Interrupt automatically becomes the highest priority level 2 interrupt, regardless of its location in the interrupt table prior to being declared as Fast Interrupt. Fast Interrupt 0 has priority over ...
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IRQ Pending (PENDING)—Bits 16–2 These register bit values represent the pending IRQs for interrupt vector numbers 2 through 16. Ascending IRQ numbers correspond to ascending bit locations. • IRQ pending for this vector number • ...
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IRQ Pending Register 3 (IRQP3) Base + $ Read Write RESET Figure 5-20 IRQ Pending Register 3 (IRQP3) 5.6.18.1 IRQ Pending (PENDING)—Bits 63–49 These register bit values represent the pending IRQs for interrupt ...
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Table 5-4 Interrupt Priority Encoding IPIC_VALUE[1: 5.6.19.3 Vector Number - Vector Address Bus (VAB)—Bits 12–6 This read-only field shows bits [7:1] of the Vector Address Bus used at the time the last IRQ was taken. In ...
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Description of Reset Operation 5.7.2.1 Reset Handshake Timing The ITCN provides the 56800E core with a reset vector address on the VAB pins whenever RESET is asserted from the SIM. The reset vector will be presented until the second ...
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Features The SIM has the following features: • Chip reset sequencing • Core and peripheral clock control and distribution • Stop/Wait mode control • System status control • Registers containing the JTAG ID of the chip • Controls for ...
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Register Descriptions A write to an address without an associated register is an NOP. A read from an address without an associated register returns unknown data. Table 6-1 SIM Registers (SIM_BASE = $00 F100) Register Base Address + Acronym ...
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Add. Address Offset Acronym SIM_ $0 CTRL SIM_ $1 RSTAT SIM_SWC0 SIM_SWC1 SIM_SWC2 SIM_SWC3 ...
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Reserved 0 = Read as 0 Figure 6-1 SIM Register Map Summary 6.3.1 SIM Control Register (SIM_CTRL) Base + $ Read Write RESET Figure 6-2 SIM Control Register (SIM_CTRL) 6.3.1.1 Reserved—Bits ...
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SIM Reset Status Register (SIM_RSTAT) This read-only register is updated upon any system reset and indicates the cause of the most recent reset. It indicates whether the COP reset vector or regular reset vector (including Power-On Reset, External Reset, ...
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Reserved—Bits 1–0 This bit field is reserved. Each bit must be set to 0. 6.3.3 SIM Software Control Registers (SIM_SWC0, SIM_SWC1, SIM_SWC2, and SIM_SWC3) These registers are general-purpose registers. They are reset only at power-on, so they can monitor ...
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SIM Power Control Register (SIM_PWR) This register controls the Standby mode of the large on-chip regulator. The large on-chip regulator derives the core digital logic power supply from the IO power supply system bus frequency of 200kHz, ...
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Reserved—Bits 15–10 This bit field is reserved. Each bit must be set to 0. 6.3.7.2 PWM3—Bit 9 • Peripheral output function of GPIOA[3] is defined to be PWM3 • Peripheral output function of GPIOA[3] is ...
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Quad Timer A Clock Rate (TMRA_CR)—Bit 14 This bit selects the clock speed for the Quad Timer A module. • Quad Timer A clock rate equals the system clock rate maximum 32MHz (default) • 1 ...
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Digital-to-Analog Clock Enable 1 (DAC1)—Bit 13 • The clock is not provided to the DAC1 module (the DAC1 module is disabled) • The clock is enabled to the DAC1 module 6.3.9.4 Digital-to-Analog Clock Enable 0 ...
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The clock is enabled to the PWM module 6.3.10 Peripheral Clock Enable Register 1 (SIM_PCE1) See Section 6.3.9 for general information about Peripheral Clock Enable registers. Base + $ Read 0 PIT2 PIT1 Write ...
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Quad Timer A, Channel 0 Clock Enable (TA0)—Bit 0 • The clock is not provided to the Timer A0 module (the Timer A0 module is disabled) • The clock is enabled to the Timer A0 ...
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The clock is enabled during Stop mode if the clock to this peripheral is enabled in the SIM_PCE0 register 6.3.11.5 Reserved—Bit 11 This bit field is reserved. It must be set to 0. 6.3.11.6 Analog-to-Digital Converter Clock ...
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Stop Disable Register 1 (SD1) See Section 6.3.11 for general information about Stop Disable Registers. Base + $ Read PIT2_ PIT1_ SD SD Write RESET Figure 6-13 Stop Disable Register 1 (SD1) ...
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Quad Timer A, Channel 1 Clock Stop Disable (TA1_SD)—Bit 1 • The clock is disabled during Stop mode • The clock is enabled during Stop mode if the clock to this peripheral is enabled in ...
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Base + $ Read Write RESET Figure 6-15 I/O Short Address Location High Register (SIM_IOSAHI) 6.3.13.1 Reserved—Bits 15—2 This bit field is reserved. Each bit must be set to 0. 6.3.13.2 ...
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Base + $ Read Write RESET Figure 6-17 Protection Register (SIM_PROT) 6.3.15.1 Reserved—Bits 15–4 This bit field is reserved. Each bit must be set to 0. 6.3.15.2 Peripheral Clock Enable Protection ...
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SIM_GPSA0 Register PWM FAULT0 Timer A0 Figure 6-18 Overall Control of Signal Source Using SIM_GPSnn Control In some cases, the user can choose peripheral function between several I/O, each of which have the option to be programmed to control a ...
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FAULT2 - PWM FAULT2 Input • TA3 - Timer A3 • Reserved 6.3.16.4 Configure GPIOA4 (GPS_A4)—Bits 9–8 This field selects the alternate function for GPIOA4. • PWM4 - PWM4 (default) • ...
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FAULT2 - PWM FAULT2 Input (default) • TA3 - Timer A3 • CMPBI1 - Comparator B Input 1 • Reserved 6.3.17.6 Configure GPIOA8 (GPS_A8)—Bits 1–0 This field selects the alternate function ...
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Configure GPIOB3 (GPS_B3)—Bits 7–6 This field selects the alternate function for GPIOB3. • MOSI0 - QSPI0 Master Out/Slave In (default) • TA3 - Timer A3 • PSRC1 - PWM2/PWM3 Pair External Source • ...
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Reserved—Bits 15–9 This bit field is reserved. Each bit must be set to 0. 6.3.19.2 Configure GPIOB11 (GPS_B11)—Bit 8 This field selects the alternate function for GPIOB11. • CMPBO - Comparator B Output (default) • ...
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XTAL - External Crystal Oscillator Output (default) • CLKIN - External Clock Input 6.3.20.3 Reserved—Bits 11–0 This bit field is reserved. Each bit must be set to 0. 6.3.21 Internal Peripheral Source Select Register 0 ...
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Base + $ Read 0 0 IPS0_ FAULT2 Write RESET Figure 6-25 Internal Peripheral Source Select Register for PWM (SIM_IPS0) 6.3.21.1 Reserved—Bits 15–14 This bit field is reserved. Each bit must be set to ...
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Reserved • 1x1 = Reserved 6.3.21.7 Select Peripheral Input Source for PWM2/PWM3 Pair Source (IPS0_PSRC1)—Bits 5–3 This field selects the alternate input source signal to feed PWM input PSRC1 as the PWM2/PWM3 pair source. • 000 = ...
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Base + $ Read Write RESET Figure 6-26 Internal Peripheral Source Select Register for DACs (SIM_IPS1) 6.3.22.1 Reserved—Bits 15–7 This bit field is reserved. Each bit must be set to 0. ...
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Base + $ Read Write RESET Figure 6-27 Internal Peripheral Source Select Register for TMRA (SIM_IPS2) 6.3.23.1 Reserved—Bits 15–13 This bit field is reserved. Each bit must be set to 0. ...
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A 3X system high-speed peripheral clock input from OCCS operates at three times the system clock at a maximum of 96MHz and can be an ...
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Power-Saving Modes The 56F8035/56F8025 operates in one of five Power-Saving modes, as shown in Table 6-2 Clock Operation in Power-Saving Modes Mode Core Clocks Run Core and memory clocks enabled Wait Core and memory clocks disabled Stop Master clock ...
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Stop mode. By asserting a peripheral’s Stop disable bit, the peripheral clock continues to operate in Stop mode. This is useful to generate interrupts which will recover the device from Stop mode to Run mode. Standby mode ...
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POR Power-On pulse shaper Reset Delay 64 (active low) OSC_CLK Clock External RESET RESET IN (active low) COP_TOR (active low) SW Reset COP_LOR (active low) Delay blocks assert immediately and deassert only after the programmed number of clock cycles. Figure ...
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The deassertion sequence of internal resets coordinates the device start up, including the clocking system start up. The sequence is described in the following steps power is applied, the Relaxation Oscillator starts to operate. When a valid operating ...
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Maximum Delay = 64 OSC_CLK cycles for POR reset extension and 32 OSC_CLK cycles RST MSTR_OSC CKGEN_RST 2X SYS_CLK SYS_CLK SYS_CLK_D SYS_CLK_DIV2 PERIP_RST CORE_RST Figure 6-29 Timing Relationships of Reset Signal to Clocks 6.8 Interrupts The SIM generates no interrupts. ...
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EOnCE debug capabilities. Normal program execution is otherwise unaffected. 7.2 Flash Access Lock and Unlock Mechanisms There are several methods that effectively lock or unlock the on-chip flash. 7.2.1 Disabling ...
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Power-on reset will also reset both. The user is responsible for directing the device to invoke the flash programming subroutine to reprogram the word $0000 into program memory location $00 7FF7. This ...
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Table 8-2 GPIO External Signals Map GPIO Function Peripheral Function GPIOA0 PWM0 GPIOA1 PWM1 GPIOA2 PWM2 GPIOA3 PWM3 GPIOA4 PWM4 / TA2 / FAULT1 GPIOA5 PWM5 / TA3 / FAULT2 GPIOA6 FAULT0 / TA0 GPIOA7 RESET GPIOA8 FAULT1 / TA2 ...
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Table 8-2 GPIO External Signals Map (Continued) GPIO Function Peripheral Function GPIOB3 MOSI0 / TA3 / PSRC1 GPIOB5 TA1 / FAULT3 / CLKIN GPIOB6 RXD0 / SDA / CLKIN GPIOB7 TXD0 / SCL GPIOB10 CMPAO GPIOB11 CMPBO GPIOC0 ANA0 / ...
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Table 8-2 GPIO External Signals Map (Continued) GPIO Function Peripheral Function GPIOD0 TDI GPIOD1 TDO GPIOD2 TCK GPIOD3 TMS GPIOD4 EXTAL GPIOD5 XTAL / CLKIN 8.3 Reset Values Tables 8-1 and 8-2 detail registers for the 56F8035/56F8025; Figures maps and ...
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Add. Register Acronym 15 Offset GPIOA_PUPEN GPIOA_DATA GPIOA_DDIR GPIOA_PEREN GPIOA_IASSRT W RS ...
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Add. Register Acronym 15 Offset GPIOB_PUPEN GPIOB_DATA GPIOB_DDIR GPIOB_PEREN GPIOB_IASSRT ...
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Add. Register Acronym 15 Offset GPIOC_PUPEN GPIOC_DATA GPIOC_DDIR GPIOC_PEREN GPIOC_IASSRT ...
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Add. Register Acronym 15 Offset R $0 GPIOD_PUPEN GPIOD_DATA GPIOD_DDIR GPIOD_PEREN GPIOD_IASSRT GPIOD_IEN W RS ...
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Part 9 Joint Test Action Group (JTAG) 9.1 56F8035/56F8025 Information Please contact your Freescale sales representative or authorized distributor for device/package-specific BSDL information. The TRST pin is not available in this package. The pin is tied to V The JTAG ...
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Table 10-1 Absolute Maximum Ratings Characteristic Supply Voltage Range Analog Supply Voltage Range ADC High Voltage Reference Voltage difference DDA Voltage difference SSA Digital Input Voltage Range Oscillator Voltage Range Analog Input ...
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Table 10-2 56F8035/56F8025 ESD Protection Characteristic ESD for Machine Model (MM) ESD for Charge Device Model (CDM) Table 10-3 LQFP Package Thermal Characteristics Characteristic Junction to ambient Natural convection Junction to ambient Natural convection Junction to ambient (@200 ft/min) Junction ...
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Table 10-4 Recommended Operating Conditions Characteristic Supply voltage ADC Reference Voltage High Voltage difference DDA Voltage difference SSA Device Clock Frequency Using relaxation oscillator Using external clock source Input Voltage High (digital ...
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DC Electrical Characteristics Table 10-5 DC Electrical Characteristics Characteristic Output Voltage High Output Voltage Low Digital Input Current High (a) pull-up enabled or disabled Comparator Input Current High Oscillator Input Current High 1 Digital Input Current Low pull-up enabled ...
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Figure 10-1 I Table 10-6 Current Consumption per Power Supply Pin Mode RUN 32MHz Device Clock Relaxation Oscillator on PLL powered on Continuous MAC instructions ...
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Table 10-6 Current Consumption per Power Supply Pin (Continued) Mode STANDBY > STOP 100kHz Device Clock Relaxation Oscillator in Standby mode PLL powered off Processor Core in STOP state All peripheral module and core clocks are off ADC/DAC/Comparator powered off ...
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The output voltage can be measured directly on the V CAP Characteristic Short Circuit Current Short Circuit Tolerance (V shorted to ground) CAP 10.3 AC Electrical Characteristics Tests are conducted using ...
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Flash Memory Characteristics Characteristic 1 Program time 2 Erase time Mass erase time 1. There is additional overhead which is part of the programming sequence. See the 56F802x and 56F803x Peripheral Reference Manual for details. 2. Specifies page erase ...
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Phase Locked Loop Timing Characteristic External reference crystal frequency for the PLL Internal reference relaxation oscillator frequency for the PLL 2 PLL output frequency (24 x reference frequency) 3 PLL lock time Accumulated jitter using an 8MHz external crystal ...
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Relaxation Oscillator Timing Table 10-12 Relaxation Oscillator Timing Characteristic Relaxation Oscillator output frequency Normal Mode Standby Mode Relaxation Oscillator stabilization time Cycle-to-cycle jitter. This is measured on the CLKO signal (programmed prescaler_clock) over 264 clocks Minimum tuning step size ...
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Reset, Stop, Wait, Mode Select, and Interrupt Timing . Table 10-13 Reset, Stop, Wait, Mode Select, and Interrupt Timing Characteristic Minimum RESET Assertion Duration Minimum GPIO pin Assertion for Interrupt RESET deassertion to First Address Fetch Delay from Interrupt ...
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Serial Peripheral Interface (SPI) Timing Characteristic Cycle time Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SCK) high time Master Slave Clock (SCK) low time Master Slave Data set-up time required for inputs Master ...
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Parameters listed are guaranteed by design. SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) t MISO (Input) MOSI (Output) Figure 10-7 SPI Master Timing (CPHA = 0) Freescale Semiconductor SS is held High on master ...
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SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) MISO (Input) (ref MOSI (Output) Figure 10-8 SPI Master Timing (CPHA = 1) 136 SS is held High on master ...
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SS (Input) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input) MISO (Output MOSI (Input) Figure 10-9 SPI Slave Timing (CPHA = 0) Freescale Semiconductor ELD ...
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SS (Input) SCLK (CPOL = 0) (Input) SCLK (CPOL = 1) (Input MISO (Output) MOSI (Input) Figure 10-10 SPI Slave Timing (CPHA = 1) 10.10 Quad Timer Timing Characteristic Timer input period Timer input high / low period ...
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Timer Inputs Timer Outputs Freescale Semiconductor P INHL OUTHL OUT Figure 10-11 Timer Timing 56F8035/56F8025 Data Sheet, Rev. 6 Quad Timer Timing P INHL P OUTHL 139 ...
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Serial Communication Interface (SCI) Timing Characteristic 2 Baud Rate 3 RXD Pulse Width 4 TXD Pulse Width Deviation of slave node clock from nominal clock rate before synchronization Deviation of slave node clock relative to the master node clock ...
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Inter-Integrated Circuit Interface (I Characteristic Symbol SCL Clock Frequency Hold time (repeated) t HD; STA START condition. After this period, the first clock pulse is generated. LOW period of the SCL clock HIGH period of the SCL t clock ...
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SDA LOW SCL t HD; STA S t HD; DAT Figure 10-14 Timing Definition for Fast and Standard Mode Devices on the I 142 SU; DAT t SU; STA SR t HIGH ...
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JTAG Timing Characteristic 1 TCK frequency of operation TCK clock pulse width TMS, TDI data set-up time TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO tri-state 1. TCK frequency of operation must ...
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Analog-to-Digital Converter (ADC) Parameters Parameter DC Specifications Resolution ADC internal clock Conversion range 2 ADC power-up time Recovery from auto standby Conversion time Sample time Accuracy 4 Integral non-linearity (Full input signal range) Differential non-linearity Monotonicity Offset Voltage Internal ...
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LSB = Least Significant Bit = 0.806mV 6. Pin groups are detailed following Table 7. The current that can be injected or sourced from an unselected ADC signal input without impacting the performance of the ADC. 10.15 Equivalent Circuit ...
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Comparator (CMP) Parameters Characteristic Conditions/Comments 1 Within range of V Input Offset Voltage Input Propagation Delay Power-up time 1. No guaranteed specification within 0. 10.17 Digital-to-Analog Converter (DAC) Parameters Parameter Conditions/Comments DC Specifications Resolution Conversion time Conversion ...
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Table 10-21 DAC Parameters (Continued) Parameter Conditions/Comments AC Specifications Signal-to-noise ratio Spurious free dynamic range Effective number of bits 1. No guaranteed specification within LSB = 0.806mV Freescale Semiconductor Symbol Min SNR SFDR ENOB or V ...
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Power Consumption See Section 10.1 for a list of IDD requirements for the 56F8035/56F8025. This section provides additional detail which can be used to optimize power consumption for a given application. Power consumption is given by the following equation: ...
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Cload is expressed in pF Because of the low duty cycle on most device pins, power dissipation due to capacitive loads was found to be fairly low when averaged over a period of time. E, the external [static component], ...
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GPIOB6 / RXD0 / SDA / CLKIN GPIOB1 / SS0 / SDA GPIOB7 / TXD0 / SCL GPIOB5 / TA1 / FAULT3 / CLKIN GPIOA9 / FAULT2 / TA3 / CMPBI1 GPIOA11 / CMPBI2 GPIOC4 / ANB0 & CMPBI3 GPIOC5 ...
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Table 11-1 56F8035/56F8025 44-Pin LQFP Package Identification by Pin Number Pin Pin Signal Name # # 1 GPIOB6 12 RXD0 / SDA / CLKIN 2 GPIOB1 13 SS0 / SDA 3 GPIOB7 14 TXD0 / SCL 4 GPIOB5 15 TA1 ...
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Figure 11-2 56F8035/56F8025 44-Pin LQFP Mechanical Information ( Please see www.freescale.com for the most current case outline. 152 56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor ...
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Figure 11-3 56F8035/56F8025 44-Pin LQFP Mechanical Information ( Please see www.freescale.com for the most current case outline. Freescale Semiconductor 56F8035/56F8025 Package and Pin-Out Information 56F8035/56F8025 Data Sheet, Rev. 6 153 ...
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Figure 11-4 56F8035/56F8025 44-Pin LQFP Mechanical Information ( Please see www.freescale.com for the most current case outline. 154 56F8035/56F8025 Data Sheet, Rev. 6 Freescale Semiconductor ...
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Part 12 Design Considerations 12.1 Thermal Design Considerations An estimation of the chip junction temperature where Ambient temperature for the package ( ...
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The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small ...
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... Electrical Design Considerations , and V pins SSA and V SS SSA and V traces. DDA SSA 2 C, the less than 0V. If positive in Ambient Temperature Order Number (MHz) Range 32 -40° 105° C MC56F8035VLD* 32 -40° 105° C MC56F8025VLD* 32 -40° 125° C MC56F8025MLD* are 157 ...
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Part 14 Appendix Register acronyms are revised from previous device data sheets to provide a cleaner register description. A cross reference to legacy and revised acronyms are provided in the following table. Table 14-1 Legacy and Revised Acronyms Peripheral Reference ...
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Table 14-1 Legacy and Revised Acronyms (Continued) Peripheral Reference Manual Register Name New Acronym Control Register CTRL Target Address TAR Register Slave Address SAR Register Data Buffer & DATA Command Register Standard Speed SSHCNT Clock SCL High Count Register Standard ...
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Table 14-1 Legacy and Revised Acronyms (Continued) Peripheral Reference Manual Register Name New Acronym Clear Receive Done CLRRXDONE Interrupt Register Clear Activity Interrupt CLRACT Register Clear Stop Detect CLRSTPDET Interrupt Register Clear Start Detect CLRSTDET Interrupt Register Clear General Call ...
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... Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc. 2010. All rights reserved. MC56F8025 Rev. 6 ...