MC74HCT125A ON Semiconductor, MC74HCT125A Datasheet - Page 2

• Manufacturer Part Number: MC74HCT125A
• Description: Quad 3-state Noninverting Buffer With Lsttl Compatible Inputs High?performance Silicon?gate Cmos
• Manufacturer: ON Semiconductor

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
Symbol
Symbol
V
in
V
V
V
T
t
I
I
V
P
T
, V
T
r
I
out
CC
CC
out
stg
CC
, t
in
in
D
A
L
f
out
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
Power Dissipation in Still Air
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage
(Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time
(Figure 1)
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
(Plastic DIP, SOIC or TSSOP Package)
Parameter
Parameter
CC
and GND Pins
TSSOP Package†
SOIC Package†
Plastic DIP†
V
V
V
CC
CC
CC
= 2.0 V
= 4.5 V
= 6.0 V
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– 0.5 to V
– 0.5 to V
2
– 55
Min
2.0
– 0.5 to + 7.0
– 65 to + 150
0
0
0
0
Value
± 20
± 35
± 75
750
500
450
260
CC
CC
+ 125
1000
Max
V
500
400
6.0
+ 0.5
+ 0.5
CC
Unit
Unit
mW
mA
mA
mA
_C
_C
_C
ns
V
V
V
V
V
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
V
range GND v (V
tied to an appropriate logic voltage
level (e.g., either GND or V
Unused outputs must be left open.
out
This device contains protection
Unused inputs must always be
should be constrained to the
in
or V
out
) v V
in
CC
CC
and
.
).