LMX2487 National Semiconductor Corporation, LMX2487 Datasheet - Page 28

• Manufacturer Part Number: LMX2487
• Description: 3.0 Ghz - 6.0 Ghz High Performance Delta-sigma Low Power Dual Pllatinum? Frequency Synthesizers With 3.0 Ghz Integer Pll
• Manufacturer: National Semiconductor Corporation

www.national.com
REGISTER
Programming Description
2.3 R2 REGISTER
2.3.1 IF_N[18:0] -- IF N Divider Value
IF_N Counter Programming with the 8/9 Prescaler (IF_P=0)
Operation with the 16/17 Prescaler (IF_P=1)
2.3.4 IF_PD -- IF Power Down Bit
When this bit is set to 0, the IF PLL operates normally. When it is set to 1, the IF PLL powers down and the output of the IF PLL
charge pump is set to a TRI-STATE mode. If the ATPU bit is set and register R0 is written to, the IF_PD will be reset to 0 and the
IF PLL will be powered up. If the CE pin is held low, the IF PLL will be powered down, overriding the IF_PD bit.
N Value
524287
N Value
48-239
262143
R2
24-55
≤47
240
241
≤23
...
56
57
...
IF_PD
0
0
1
.
0
0
1
23
.
48-51, 64-68, 80-85, 96-102, 112-119, 128-136, 144-153, 160-170, 176-187, 192-204, 208-221, 224-238
0
0
1
.
0
0
1
.
22
0
0
1
.
0
0
1
21
.
N values less than or equal to 47 are prohibited because IF_B ≥ 3 is required.
N values less than or equal to 23 are prohibited because IF_B ≥ 3 is required.
0
0
1
20
.
0
0
1
.
19
0
0
1
.
0
0
1
.
18
0
0
1
.
0
0
1
.
(Continued)
17
0
0
1
.
0
0
1
Legal divide ratios in this range are:
.
Legal divide ratios in this range are:
16
IF_B
DATA[19:0]
IF_B
24-27, 32-36, 40-45, 48-54
0
0
1
.
0
0
1
15
.
IF_N[18:0]
14
0
0
1
.
0
0
1
28
.
IF_N[18:0]
13
0
0
1
.
0
0
1
.
12
0
0
1
.
0
0
1
.
11
1
1
1
.
0
0
1
.
10
1
1
1
.
9
1
1
1
.
8
1
1
1
1
1
1
.
.
7
6
1
1
1
.
1
1
1
.
5
0
0
1
0
0
0
.
.
4
C3
3
0
0
0
1
0
0
1
.
.
IF_A
IF_A
C2
2
1
0
0
1
0
0
1
.
.
C1
1
0
0
1
1
0
1
1
.
.
C0
0
1