ADL5541 Analog Devices, Inc., ADL5541 Datasheet - Page 10

• Manufacturer Part Number: ADL5541
• Description: 50 Mhz To 6 Ghz Rf/if Gain Block
• Manufacturer: Analog Devices, Inc.

ADL5541
BASIC CONNECTIONS
The basic connections for operating the ADL5541 are shown in
Figure 13. Recommended components are listed in Table 5. The
input and output should be ac-coupled with appropriately sized
capacitors (device characterization was performed with 33 pF
capacitors). A 5 V dc bias is supplied to the amplifier via GND
(Pin 6) and through a biasing inductor connected to RFOUT
(Pin 8). The bias voltage should be decoupled using a 1 μF
capacitor, a 1.2 nF capacitor, and two 68 pF capacitors.
For operation between 50 MHz and 500 MHz, a larger biasing
choke and ac coupling capacitors are necessary (see Table 5).
Figure 14 shows a plot of the input return loss, the output
return loss and the gain with these components. At 100 MHz,
the ADL5541 achieves an OIP3 of 38 dBm (P
tone). The noise figure performance for operation from 50
MHz to 500 MHz is shown in Figure 15. When operating below
50 MHz, the ADL5541 exhibits gain peaking, and the input and
output match degrade significantly.
Table 5. Recommended Components for Basic Connections
Frequency
50 MHz to 500 MHz
500 MHz to 6000 MHz
RFIN
17.0
16.5
16.0
15.5
15.0
14.5
14.0
13.5
13.0
12.5
12.0
Figure 14. Input Return Loss (S11), Output Return Loss (S22), and
50
VCC
100
33pF
1µF
C1
C3
150
C6
1µF
S21
Figure 13. Basic Connections
1 RFIN
2 GND
3 GND
4 CB
Gain (S21) vs. Frequency
200
ADL5541
FREQUENCY (MHz)
C1
0.1 μF
33 pF
C5
1.2nF
RFOUT
250
VPOS
GND
GND
S22
300
8
7
6
5
C2
0.1 μF
33 pF
C4
68pF
350
C7
68pF
L1
47nH
VCC
400
GND
OUT
C3
1 μF
1 μF
33pF
S11
C2
= 0 dBm per
450
L1
470 nH (Coilcraft 0603LS-471-NX or equivalent)
47 nH (Coilcraft 0603CS-47-NX or equivalent)
500
–5
–10
–15
–20
–25
–30
RFOUT
Rev. 0 | Page 10 of 12
SOLDERING INFORMATION AND RECOMMENDED
PCB LAND PATTERN
Figure 16 shows the recommended land pattern for the ADL5541.
To minimize thermal impedance, the exposed paddle on the
package underside should be soldered down to a ground plane
along with Pin 2, Pin 3, Pin 6, and Pin 7. If multiple ground
layers exist, they should be stitched together using vias (a
minimum of five vias is recommended). For more information
on land pattern design and layout, refer to Application Note
AN-772, A Design and Manufacturing Guide for the Lead Frame
Chip Scale Package (LFCSP).
0.5mm
Figure 15. Noise Figure vs. Frequency from 50 MHz to 500 MHz
4.5
4.0
3.5
3.0
2.5
2.0
50
0.71mm
PIN 1
PIN 4
100
Figure 16. Recommended Land Pattern
150
200
FREQUENCY (MHz)
2.03mm
1.53mm
250
C4
68 pF
68 pF
1.85mm
300
350
C5
1.2 nF
1.2 nF
PIN 8
PIN 5
400
C6
1 μF
1 μF
450
1.78mm
500
C7
68 pF
68 pF