DSPIC33FJ12GP202 Microchip Technology Inc., DSPIC33FJ12GP202 Datasheet
DSPIC33FJ12GP202
Available stocks
Related parts for DSPIC33FJ12GP202
DSPIC33FJ12GP202 Summary of contents
Page 1
... Microchip Technology Inc. dsPIC33FJ12GP201/202 High-Performance, 16-Bit Digital Signal Controllers Preliminary Data Sheet DS70264B ...
Page 2
... Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. Preliminary , K L logo, microID, MPLAB, PIC DSCs code hopping ® ® © 2007 Microchip Technology Inc. ...
Page 3
... On-Chip Flash and SRAM: • Flash program memory (12 Kbytes) • Data SRAM (1024 bytes) • Boot and General Security for Program Flash © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 Digital I/O: • Peripheral Pin Select Functionality • programmable digital I/O pins • ...
Page 4
... Fully static design • 3.3V (±10%) operating voltage • Industrial and extended temperature • Low power consumption Packaging: • 18-pin SDIP/SOIC • 28-pin SDIP/SOIC/QFN Note: See the device variant tables for exact peripheral features per device. Preliminary © 2007 Microchip Technology Inc. ...
Page 5
... The device names, pin counts, memory sizes and peripheral availability of each family are listed below, followed by their pinout diagrams. TABLE 1: dsPIC33FJ12GP201/202 CONTROLLER FAMILIES Device dsPIC33FJ12GP201 18 12 dsPIC33FJ12GP202 28 12 Note 1: Only 2 out of 3 timers are remappable. © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 Remappable Peripherals (1) ...
Page 6
... SDIP/SOIC Package Diagram 18-PIN SDIP, SOIC PGD2/EMUD2/AN0/VREF+/CN2/RA0 PGC2/EMUC2/AN1/VREF-/CN3/RA1 PGD1/EMUD1/AN2/RP0/CN4/RB0 PGC1/EMUC1/AN3/RP1/CN5/RB1 OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 PGD3/EMUD3/SOSCI/RP4/CN1/RB4 PGC3/EMUC3/SOSCO/T1CK/CN0/RA4 Pin Diagrams dsPIC33FJ12GP202 28-Pin SDIP/SOIC Package Diagram 28-PIN SDIP, SOIC PGD2/EMUD2/AN0/VREF+/CN2/RA0 PGC2/EMUC2/AN1/VREF-/CN3/RA1 PGD1/EMUD1/AN2/RP0/CN4/RB0 PGC1/EMUC1/AN3/RP1/CN5/RB1 AN4/RP2/CN6/RB2 AN5/RP3/CN7/RB3 OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 PGD3/EMUD3/SOSC/RP4/CN1/RB4 PGC3/EMUC3/SOSCO/T1CK/CN0/RA4 ...
Page 7
... QFN Package Diagram 28-Pin QFN 6x6mm PGD1/EMUD1/AN2/RP0/CN4/RB0 PGC1/EMUC1/AN3/RP1/CN5/RB1 AN4/RP2/CN6/RB2 AN5/RP3/CN7/RB3 V SS OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 AN8/RP13/CN13/RB13 21 AN9/RP12/CN14/RB12 TMS/RP11/CN15/RB11 dsPIC33FJ12GP202 4 18 TDI/RP10/CN16/RB10 DDCORE TDO/SDA1/RP9/CN21/RB9 ...
Page 8
... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS70264B-page 6 Preliminary © 2007 Microchip Technology Inc. ...
Page 9
... Figure 1-1 shows a general block diagram of the core and peripheral modules dsPIC33FJ12GP201/202 family of devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams. © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 the latest Manual in the Preliminary DS70264B-page 7 ...
Page 10
... Latch Latch Control Logic 16 16 Address Generator Units EA MUX ROM Latch 16 Instruction Reg DSP Engine Register Array Divide Support 16-bit ALU MCLR OC/ UART1 ADC1 PWM1-2 CNx I2C1 Preliminary PORTA PORTB 16 Remappable Pins © 2007 Microchip Technology Inc. ...
Page 11
... PGC3/EMUC3 I ST Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 Description Analog input channels. External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode ...
Page 12
... Analog voltage reference (low) input. Positive supply for analog modules. Master Clear (Reset) input. This pin is an active-low Reset to the device. Ground reference for analog modules. Positive supply for peripheral logic and I/O pins. Analog = Analog input O = Output Preliminary P = Power I = Input © 2007 Microchip Technology Inc. ...
Page 13
... X mem- ory AGU, which accesses the entire memory map as one linear data space. Certain DSP instructions operate © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 through the X and Y AGUs to support dual operand reads, which splits the data address space into two parts. The X and Y data space boundary is device-specific ...
Page 14
... PCH PCL X RAM Y RAM Address Address Loop Control Latch Latch Logic 16 16 Address Generator Units EA MUX ROM Latch 16 Instruction Reg DSP Engine Register Array Divide Support Preliminary 16-bit ALU 16 To Peripheral Modules © 2007 Microchip Technology Inc. ...
Page 15
... Accumulators ACCB PC22 0 7 TBLPAG Data Table Page Address 7 0 PSVPAG 22 DOSTART OAB SAB DA SRH © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM ...
Page 16
... IPL<3> The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>). DS70264B-page 14 R/C-0 R-0 (1) (1) SB OAB (3) R-0 R/W Unimplemented bit, read as ‘0’ Value at POR x = Bit is unknown (1) (1) Preliminary R/C R/W-0 SAB DA DC bit 8 R/W-0 R/W-0 R/W bit 0 © 2007 Microchip Technology Inc. ...
Page 17
... The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL<3> User interrupts are disabled when IPL<3> The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>). © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 (2) Preliminary DS70264B-page 15 ...
Page 18
... The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. DS70264B-page 16 R/W-0 R/W-0 R-0 (1) US EDT R/W-0 R/C-0 R/W-0 (2) ACCSAT IPL3 PSV -n = Value at POR U = Unimplemented bit, read as ‘0’ (1) (2) Preliminary R-0 R-0 DL<2:0> bit 8 R/W-0 R/W-0 RND IF bit 0 ‘1’ = Bit is set © 2007 Microchip Technology Inc. ...
Page 19
... CLR ED EDAC MAC MAC MOVSAC MPY MPY MPY.N MSC © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 1. 32-bit signed/16-bit signed divide 2. 32-bit unsigned/16-bit unsigned divide 3. 16-bit signed/16-bit signed divide 4. 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends and the remainder in W1 ...
Page 20
... FIGURE 2-3: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In DS70264B-page 18 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Preliminary Round u Logic Zero Backfill © 2007 Microchip Technology Inc. ...
Page 21
... The adder/subtracter is a 40-bit adder with an optional zero input into one side, and either true or complement data into the other input. © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 • In the case of addition, the Carry/Borrow input is active-high and the other input is true data (not complemented). • ...
Page 22
... Section 2.6.2.4 “Data Space Write Saturation”). For the MAC class of instructions, the accumulator write-back operation functions in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding. Preliminary © 2007 Microchip Technology Inc. to data saturation (see ...
Page 23
... If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 2.6.3 BARREL SHIFTER The barrel shifter can perform up to 16-bit arithmetic or logic right shifts 16-bit left shifts in a single cycle ...
Page 24
... NOTES: DS70264B-page 22 Preliminary © 2007 Microchip Technology Inc. ...
Page 25
... This architecture also allows the direct access of program memory from the data space during code execution. FIGURE 3-1: PROGRAM MEMORY FOR dsPIC33FJ12GP201/202 DEVICES © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 3.1 Program Address Space The program dsPIC33FJ12GP201/202 devices is 4M instructions ...
Page 26
... Interrupt Service Routines (ISRs). A more detailed discussion of the interrupt vector tables is provided in Section 6.1 “Interrupt Vector Table”. least significant word Instruction Width Preliminary PC Address (lsw Address) 0 0x000000 0x000002 0x000004 0x000006 © 2007 Microchip Technology Inc. ...
Page 27
... Data byte writes only write to the corresponding side of the array or register that matches the byte address. © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word opera- tions, or translating from 8-bit MCU code ...
Page 28
... Optionally Mapped into Program Memory 0xFFFF DS70264B-page 26 LSB 16 bits Address MSb LSb 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x09FE 0x0A00 Y Data RAM (Y) 0x0BFE 0x0C00 0x1FFFF 0x2000 0x8000 X Data Unimplemented (X) 0xFFFE Preliminary 8-Kbyte Near Data Space © 2007 Microchip Technology Inc. ...
Page 29
... All effective addresses are 16 bits wide and point to bytes within the data space. Therefore, the data space address range is 64 Kbytes, or 32K words, though the implemented memory locations vary by device. © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 Preliminary DS70264B-page 27 ...
Page 30
TABLE 3-1: CPU CORE REGISTERS MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Addr WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 0016 ...
Page 31
... TABLE 3-2: CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ12GP202 SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CNEN2 0062 CN30IE CN29IE — — CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CNPU2 006A CN30PUE CN29PUE — — Legend unknown value on Reset, — ...
Page 32
TABLE 3-4: INTERRUPT CONTROLLER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr INTCON1 0080 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE INTCON2 0082 ALTIVT DISI — — IFS0 0084 — — AD1IF U1TXIF IFS1 0086 ...
Page 33
TABLE 3-5: TIMER REGISTER MAP SFR Name SFR Bit 15 Bit 14 Bit 13 Bit 12 Addr TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON ...
Page 34
TABLE 3-8: I2C1 REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr I2C1RCV 0200 — — — — I2C1TRN 0202 — — — — I2C1BRG 0204 — — — — I2C1CON 0206 I2CEN — I2CSIDL ...
Page 35
TABLE 3-11: PERIPHERAL PIN SELECT INPUT REGISTER MAP File Addr Bit 15 Bit 14 Bit 13 Bit 12 Name RPINR0 0680 — — — RPINR1 0682 — — — — RPINR3 0686 — — — RPINR7 068E — — — ...
Page 36
TABLE 3-14: ADC1 REGISTER MAP FOR dsPIC33FJ12GP201 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ...
Page 37
... TABLE 3-15: ADC1 REGISTER MAP FOR dsPIC33FJ12GP202 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ADC1BUFB 0316 ADC1BUFC 0318 ADC1BUFD 031A ...
Page 38
... ODCA 02C6 — — — — Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-17: PORTB REGISTER MAP FOR dsPIC33FJ12GP202 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISB 02C8 TRISB15 TRISB14 TRISB13 ...
Page 39
TABLE 3-20: NVM REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 NVMCON 0760 WR WREN WRERR — NVMKEY 0766 — — — — Legend unknown value on Reset, — = unimplemented, read as ...
Page 40
... Register Indirect Post-Modified • Register Indirect Pre-Modified • 5-bit or 10-bit Literal Note: Not all instructions support all the addressing modes given above. Individual instructions can support different subsets of these addressing modes. Preliminary © 2007 Microchip Technology Inc. addressing modes are ...
Page 41
... MAC instructions, use a simplified set of addressing modes to allow the user application to effectively manipulate the data pointers through register indirect tables. © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 Description The address of the file register is specified explicitly. The contents of a register are accessed directly. ...
Page 42
... MOV #0x1110, W1 ;point W1 to buffer DO AGAIN, #0x31 ;fill the 50 buffer locations MOV W0, [W1++] ;fill the next location AGAIN: INC W0, W0 ;increment the fill value Preliminary and YMODEND (see the difference between the © 2007 Microchip Technology Inc. ...
Page 43
... The modifier, which can be a constant value or register contents, is regarded as having its bit order reversed. The address source and destination are kept in normal order. Thus, the only operand requiring reversal is the modifier. © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 3.5.1 BIT-REVERSED ADDRESSING IMPLEMENTATION ...
Page 44
... Preliminary A0 Decimal © 2007 Microchip Technology Inc. ...
Page 45
... User (Block Remap/Read) Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG<0>. © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 3.6.1 ADDRESSING PROGRAM SPACE Since the address ranges for the data and program ...
Page 46
... Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space. DS70264B-page 44 Program Counter 0 23 bits 1/0 TBLPAG 8 bits 24 bits Select 1 0 PSVPAG 8 bits 23 bits Preliminary 0 EA 1/0 16 bits bits Byte Select © 2007 Microchip Technology Inc. ...
Page 47
... ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS TBLPAG © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 In Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when Byte Select is ‘1’; the lower byte is selected when it is ‘ ...
Page 48
... PSV Area 0x800000 Preliminary 1111’ or and MOV.D instructions 0x0000 Data EA<14:0> 0x8000 ...while the lower 15 bits of the EA specify an exact address within the PSV area. This 0xFFFF corresponds exactly to the same lower 15 bits of the actual program space address. © 2007 Microchip Technology Inc. ...
Page 49
... Using 1/0 Table Instruction User/Configuration Space Select © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 then program the digital signal controller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions ...
Page 50
... Setting the WR bit (NVMCON<15>) starts the operation, and the WR bit is automatically cleared when the operation is finished. required for Preliminary the user application must to Section 4.4 “Programming © 2007 Microchip Technology Inc. ...
Page 51
... No operation 0011 = Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte Note 1: These bits can only be Reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented. © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 (1) U-0 U-0 — — (1) U-0 ...
Page 52
... Bit is set bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 NVMKEY<7:0>: Key Register (write-only) bits DS70264B-page 50 U-0 U-0 U-0 — — — W-0 W-0 W-0 NVMKEY<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. U-0 U-0 — — bit 8 W-0 W-0 bit Bit is unknown ...
Page 53
... MOV #0xAA, W1 MOV W1, NVMKEY BSET NVMCON, #WR NOP NOP © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 4. Write the first 64 instructions from data RAM into the program memory buffers (see Example 4-2). 5. Write the program block to Flash memory: a) Set the NVMOP bits to ‘0001’ to configure for row programming ...
Page 54
... Write PM low word into program latch ; Write PM high byte into program latch ; Block all interrupts with priority <7 ; for next 5 instructions ; Write the 55 key ; ; Write the AA key ; Start the erase sequence ; Insert two NOPs after the ; erase command is asserted Preliminary © 2007 Microchip Technology Inc. ...
Page 55
... DD Trap Conflict Illegal Opcode Uninitialized W Register Configuration Mismatch © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 Any active source of Reset makes the SYSRST signal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. Most registers are unaffected by a Reset; their status is unknown on POR and unchanged by all other Resets ...
Page 56
... If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. DS70264B-page 54 (1) U-0 U-0 U-0 — — R/W-0 R/W-0 R/W-0 (2) WDTO SLEEP IDLE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (2) Preliminary R/W-0 R/W-0 — CM VREGS bit 8 R/W-1 R/W-1 BOR POR bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 57
... EXTR (RCON<7>) SWR (RCON<6>) WDTO (RCON<4>) SLEEP (RCON<3>) IDLE (RCON<2>) BOR (RCON<1>) POR (RCON<0>) Note 1: All Reset flag bits may be set or cleared by the user software. © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 (1) (CONTINUED) (1) Setting Event Trap conflict event Illegal opcode or uninitialized W register access ...
Page 58
... Preliminary FSCM Notes Delay — FSCM FSCM LOCK FSCM — FSCM FSCM LOCK FSCM — 3 — 3 — 3 — 3 — 3 — 3 © 2007 Microchip Technology Inc. ...
Page 59
... FRC oscillator and the user application can switch to the desired crystal oscillator in the Trap Service Routine (TSR). © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 5.2.2.1 FSCM Delay for Crystal and PLL Clock Sources ...
Page 60
... NOTES: DS70264B-page 58 Preliminary © 2007 Microchip Technology Inc. ...
Page 61
... These are summarized in Table 6-1 and Table 6-2. © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 6.1.1 ALTERNATE INTERRUPT VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 6-1 ...
Page 62
... Note 1: See Table 6-1 for the list of implemented interrupt vectors. DS70264B-page 60 0x000000 0x000002 0x000004 0x000014 ~ ~ ~ 0x00007C Interrupt Vector Table (IVT) 0x00007E 0x000080 ~ ~ ~ 0x0000FC 0x0000FE 0x000100 0x000102 0x000114 ~ ~ ~ Alternate Interrupt Vector Table (AIVT) 0x00017C 0x00017E 0x000180 ~ ~ ~ 0x0001FE 0x000200 Preliminary (1) (1) © 2007 Microchip Technology Inc. ...
Page 63
... Microchip Technology Inc. dsPIC33FJ12GP201/202 AIVT Address Interrupt Source 0x000114 INT0 – External Interrupt 0 0x000116 IC1 – Input Compare 1 0x000118 OC1 – Output Compare 1 0x00011A T1 – Timer1 0x00011C Reserved 0x00011E IC2 – ...
Page 64
... AIVT Address 0x000004 0x000104 0x000006 0x000106 0x000008 0x000108 0x00000A 0x00010A 0x00000C 0x00010C 0x00000E 0x00010E 0x000010 0x000110 0x000012 0x000112 Preliminary Interrupt Source Trap Source Reserved Oscillator Failure Address Error Stack Error Math Error Reserved Reserved Reserved © 2007 Microchip Technology Inc. ...
Page 65
... IECx The IEC registers maintain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals. © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 6.3.4 IPCx The IPC registers are used to set the interrupt priority level for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels ...
Page 66
... U = Unimplemented bit, read as ‘0’ Value at POR x = Bit is unknown (1) (1) R/W-0 R/W-0 US EDT R/W-0 R/C-0 (2) ACCSAT IPL3 -n = Value at POR U = Unimplemented bit, read as ‘0’ (2) Preliminary R/C R/W-0 SAB DA DC bit 8 R/W-0 R/W-0 R/W bit 0 R-0 R-0 R-0 DL<2:0> bit 8 R/W-0 R/W-0 R/W-0 PSV RND IF bit 0 ‘1’ = Bit is set © 2007 Microchip Technology Inc. ...
Page 67
... MATHERR: Arithmetic Error Status bit 1 = Math error trap has occurred 0 = Math error trap has not occurred bit 3 ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 R/W-0 R/W-0 R/W-0 COVAERR COVBERR ...
Page 68
... Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ DS70264B-page 66 Preliminary © 2007 Microchip Technology Inc. ...
Page 69
... Interrupt on positive edge bit 1 INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 U-0 U-0 U-0 — — — U-0 ...
Page 70
... OC1IF: Output Compare Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70264B-page 68 R/W-0 R/W-0 R/W-0 U1TXIF U1RXIF SPI1IF U-0 R/W-0 R/W-0 — T1IF OC1IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1EIF T3IF bit 8 R/W-0 R/W-0 IC1IF INT0IF bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 71
... IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 Preliminary DS70264B-page 69 ...
Page 72
... SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70264B-page 70 U-0 U-0 U-0 — — — R/W-0 R/W-0 U-0 INT1IF CNIF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 MI2C1IF SI2C1IF bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 73
... Value at POR ‘1’ = Bit is set bit 15-2 Unimplemented: Read as ‘0’ bit 1 U1EIF: UART1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 U-0 U-0 U-0 — — — U-0 U-0 U-0 — ...
Page 74
... OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70264B-page 72 R/W-0 R/W-0 R/W-0 U1TXIE U1RXIE SPI1IE U-0 R/W-0 R/W-0 — T1IE OC1IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1EIE T3IE bit 8 R/W-0 R/W-0 IC1IE INT0IE bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 75
... IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 Preliminary DS70264B-page 73 ...
Page 76
... SI2C1IE: I2C1 Slave Events Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS70264B-page 74 U-0 U-0 U-0 — — — R/W-0 R/W-0 U-0 INT1IE CNIE — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 MI2C1IE SI2C1IE bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 77
... W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-2 Unimplemented: Read as ‘0’ bit 1 U1EIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 U-0 U-0 U-0 — — — U-0 U-0 U-0 — ...
Page 78
... Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS70264B-page 76 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 OC1IP<2:0> bit 8 R/W-0 R/W-0 INT0IP<2:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 79
... Unimplemented: Read as ‘0’ bit 6-4 IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 R/W-0 U-0 R/W-1 — R/W-0 U-0 U-0 — — ...
Page 80
... Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS70264B-page 78 R/W-0 U-0 R/W-1 — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 SPI1IP<2:0> bit 8 R/W-0 R/W-0 T3IP<2:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 81
... Interrupt source is disabled bit 3 Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 U-0 U-0 U-0 — — — R/W-0 U-0 R/W-1 — ...
Page 82
... Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS70264B-page 80 R/W-0 U-0 U-0 — — R/W-0 U-0 R/W-1 — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 SI2C1IP<2:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 83
... Interrupt source is disabled bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 R/W-0 U-0 R/W-1 — U-0 U-0 R/W-1 — — Unimplemented bit, read as ‘0’ ...
Page 84
... Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ DS70264B-page 82 U-0 U-0 U-0 — — — R/W-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 U-0 U-0 — — bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 85
... Unimplemented: Read as ‘0’ bit 6-4 U1EIP<2:0>: UART1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 U-0 U-0 U-0 — — — R/W-0 U-0 U-0 — ...
Page 86
... Interrupt Vector pending is number 135 • • • 0000001 = Interrupt Vector pending is number 9 0000000 = Interrupt Vector pending is number 8 DS70264B-page 84 U-0 R-0 R-0 — ILR<3:0> R-0 R-0 R-0 VECNUM<6:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. R-0 R-0 bit 8 R-0 R-0 bit Bit is unknown ...
Page 87
... ISR immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 6.4.3 TRAP SERVICE ROUTINE A Trap Service Routine is coded like an ISR, except that the appropriate trap status flag in the INTCON1 register must be cleared to avoid re-entry into the TSR ...
Page 88
... NOTES: DS70264B-page 86 Preliminary © 2007 Microchip Technology Inc. ...
Page 89
... Secondary Oscillator SOSCO LPOSCEN SOSCI Note 1: See Figure 7-2 for PLL details. © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 • An on-chip PLL to scale the internal operating frequency to the required system clock frequency • An internal FRC oscillator that can also be used with the PLL, thereby allowing full-speed ...
Page 90
... PLL must be selected such that the PLL output frequency ( the range of 12.5 MHz to 80 MHz, which OSC generates device operating speeds of 6.25-40 MIPS. Preliminary © 2007 Microchip Technology Inc. Configuration bits, is divided OSC ). ...
Page 91
... Fast RC Oscillator (FRC) Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit. 2: This is the default oscillator mode for an unprogrammed (erased) device. © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 ’, • If PLLDIV<8:0> = 0x1E, then M = 32. This yields a IN VCO output 160 MHz, which is within the 100-200 MHz ranged needed. • ...
Page 92
... FSCM has detected clock failure 0 = FSCM has not detected clock failure bit 2 Unimplemented: Read as ‘0’ DS70264B-page 90 R-0 U-0 R/W-y — U-0 R/C-0 U-0 — CF — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. R/W-y R/W-y NOSC<2:0> bit 8 R/W-0 R/W-0 LPOSCEN OSWEN bit Bit is unknown ...
Page 93
... OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 1 LPOSCEN: Secondary (LP) Oscillator Enable bit 1 = Enable secondary oscillator 0 = Disable secondary oscillator bit 0 OSWEN: Oscillator Switch Enable bit 1 = Request oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 Preliminary DS70264B-page 91 ...
Page 94
... Input/33 Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs. DS70264B-page 92 R/W-0 R/W-0 R/W-1 (1) DOZEN R/W-0 R/W-0 R/W-0 PLLPRE<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 FRCDIV<2:0> bit 8 R/W-0 R/W-0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 95
... PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier) 000000000 = 2 000000001 = 3 000000010 = 4 • • • 000110000 = 50 (default) • • • 111111111 = 513 © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 U-0 U-0 U-0 — — — R/W-1 R/W-0 R/W-0 PLLDIV<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 96
... Center frequency -0.375% (7.345 MHz) • • • 100001 = Center frequency -11.625% (6.52 MHz) 100000 = Center frequency -12% (6.49 MHz) DS70264B-page 94 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 TUN<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 97
... Set the OSWEN bit to initiate the oscillator switch. Once the basic sequence is completed, the system clock hardware responds automatically as follows: © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 1. The clock switching hardware compares the COSC status bits with the new value of the NOSC control bits. If they are the same, the clock switch is a redundant operation ...
Page 98
... NOTES: DS70264B-page 96 Preliminary © 2007 Microchip Technology Inc. ...
Page 99
... EXAMPLE 8-1: PWRSAV INSTRUCTION SYNTAX PWRSAV #SLEEP_MODE ; Put the device into SLEEP mode PWRSAV #IDLE_MODE ; Put the device into IDLE mode © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 8.2 Instruction-Based Power-Saving Modes dsPIC33FJ12GP201/202 devices have two special power-saving modes that are entered through the execution of a special PWRSAV instruction ...
Page 100
... Similarly PMD bit is cleared, the corresponding module is enabled after a delay of one instruction cycle (assuming the module control registers are already configured to enable module operation). Preliminary There are eight possible ® DSC © 2007 Microchip Technology Inc. ...
Page 101
... CK WR Port Data Latch Read LAT Read Port © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin can be read, but the output driver for the parallel port bit is disabled ...
Page 102
... CNPU2 registers, which contain the control bits for each of the CN pins. Setting any of the control bits enables the weak pull-ups for the corresponding pins. Note: Pull-ups on change notification pins should always be disabled when the port pin is configured as a digital output. Preliminary devices to © 2007 Microchip Technology Inc. ...
Page 103
... I/O circuitry on a specific port and cannot be easily connected to multiple pins. These modules include I A similar requirement excludes all modules with analog inputs, such as the Analog-to-Digital Converter (ADC). © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 Remappable peripherals are not associated with a default I/O pin. The peripheral must always be assigned to a specific I/O pin before it can be used ...
Page 104
... RPINR7 IC2 RPINR7 IC7 RPINR10 IC8 RPINR10 OCFA RPINR11 U1RX RPINR18 U1CTS RPINR18 SDI1 RPINR20 SCK1IN RPINR20 SS1IN RPINR21 Preliminary (1) Configuration Bits INT1R<4:0> INT2R<4:0> T2CKR<4:0> T3CKR<4:0> IC1R<4:0> IC2R<4:0> IC7R<4:0> IC8R<4:0> OCFAR<4:0> U1RXR<4:0> U1CTSR<4:0> SDI1R<4:0> SCK1R<4:0> SS1R<4:0> © 2007 Microchip Technology Inc. ...
Page 105
... U1RTS SDO1 SCK1OUT SS1OUT OC1 OC2 © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 through Register 9-17). The value of the bit field corresponds to one of the peripherals, and that peripheral’s output is mapped to the pin (see Table 9-2 and Figure 9-3). The list of peripherals for output mapping also includes a null value of 00000 technique ...
Page 106
... Because the unlock sequence is timing-critical, it must be executed as an assembly language routine, in the same manner as changes configuration. If the bulk of the application is written another high-level language, the unlock sequence should be performed by writing inline assembly. Preliminary © 2007 Microchip Technology Inc. is executed, the user to the oscillator ...
Page 107
... Configuration Example Example 9-2 shows a configuration for bidirectional communication with flow control using UART1. The following input and output functions are used: • Input Functions: U1RX, U1CTS • Output Functions: U1TX, U1RTS © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 EXAMPLE 9-2: //************************************* // Unlock Registers //************************************* asm volatile ( " ...
Page 108
... Input tied to RP1 00000 = Input tied to RP0 bit 7-0 Unimplemented: Read as ‘0’ DS70264B-page 106 R/W-1 R/W-1 R/W-1 INT1R<4:0> U-0 U-0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS Preliminary R/W-1 R/W-1 bit 8 U-0 U-0 U-0 — — — bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 109
... Unimplemented: Read as ‘0’ bit 4-0 INT2R<4:0>: Assign External Interrupt 2 (INTR2) to the corresponding RPn pin bits 11111 = Input tied to V 01111 = Input tied to RP15 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 U-0 U-0 — — R/W-1 R/W-1 R/W-1 INT2R<4:0> ...
Page 110
... Input tied to V 01111 = Input tied to RP15 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 DS70264B-page 108 R/W-1 R/W-1 R/W-1 T3CKR<4:0> R/W-1 R/W-1 R/W-1 T2CKR<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS Preliminary R/W-1 R/W-1 bit 8 R/W-1 R/W-1 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 111
... Unimplemented: Read as ‘0’ bit 4-0 IC1R<4:0>: Assign Input Capture 1 (IC1) to the corresponding RPn pin bits 11111 = Input tied to V 01111 = Input tied to RP15 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 R/W-1 R/W-1 R/W-1 IC2R<4:0> R/W-1 R/W-1 R/W-1 IC1R<4:0> ...
Page 112
... Input tied to V 01111 = Input tied to RP15 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 DS70264B-page 110 R/W-1 R/W-1 R/W-1 IC8R<4:0> R/W-1 R/W-1 R/W-1 IC7R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS Preliminary R/W-1 R/W-1 bit 8 R/W-1 R/W-1 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 113
... Unimplemented: Read as ‘0’ bit 4-0 OCFAR<4:0>: Assign Output Capture A (OCFA) to the corresponding RPn pin bits 11111 = Input tied to V 01111 = Input tied to RP15 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 U-0 U-0 — — R/W-1 R/W-1 R/W-1 OCFAR<4:0> ...
Page 114
... Input tied to V 01111 = Input tied to RP15 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 DS70264B-page 112 R/W-1 R/W-1 R/W-1 U1CTSR<4:0> R/W-1 R/W-1 R/W-1 U1RXR<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS SS Preliminary R/W-1 R/W-1 bit 8 R/W-1 R/W-1 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 115
... Unimplemented: Read as ‘0’ bit 4-0 SDI1R<4:0>: Assign SPI 1 Data Input (SDI1) to the corresponding RPn pin bits 11111 = Input tied to V 01111 = Input tied to RP15 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 R/W-1 R/W-1 R/W-1 SCK1R<4:0> R/W-1 R/W-1 R/W-1 SDI1R<4:0> ...
Page 116
... Input tied to RP15 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 DS70264B-page 114 U-0 U-0 — — R/W-1 R/W-1 R/W-1 SS1R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared SS Preliminary U-0 U-0 U-0 — — — bit 8 R/W-1 R/W-1 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 117
... RP3R<4:0>: Peripheral Output Function is Assigned to RP3 Output Pin bits (see Table 9-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP2R<4:0>: Peripheral Output Function is Assigned to RP2 Output Pin bits (see Table 9-2 for peripheral function numbers) © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 R/W-0 R/W-0 R/W-0 RP1R<4:0> R/W-0 ...
Page 118
... DS70264B-page 116 R/W-0 R/W-0 R/W-0 RP5R<4:0> R/W-0 R/W-0 R/W-0 RP4R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 RP7R<4:0> R/W-0 R/W-0 R/W-0 RP6R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 119
... RP11R<4:0>: Peripheral Output Function is Assigned to RP11 Output Pin bits (see Table 9-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP10R<4:0>: Peripheral Output Function is Assigned to RP10 Output Pin bits (see Table 9-2 for peripheral function numbers) © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 R/W-0 R/W-0 R/W-0 RP9R<4:0> R/W-0 ...
Page 120
... DS70264B-page 118 R/W-0 R/W-0 R/W-0 RP13R<4:0> R/W-0 R/W-0 R/W-0 RP12R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 RP15R<4:0> R/W-0 R/W-0 R/W-0 RP14R<4:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown R/W-0 R/W-0 bit 8 R/W-0 R/W-0 bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 121
... SOSCO/ T1CK SOSCI TGATE 1 Set T1IF 0 Reset Equal © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 Figure 10-1 presents a block diagram of the 16-bit timer module. To configure Timer1 for operation: 1. Set the TON bit (= 1) in the T1CON register. 2. Select the timer prescaler ratio using the TCKPS< ...
Page 122
... External clock from pin T1CK (on the rising edge Internal clock (F CY bit 0 Unimplemented: Read as ‘0’ DS70264B-page 120 U-0 U-0 — — R/W-0 U-0 TCKPS<1:0> — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ) Preliminary U-0 U-0 U-0 — — — bit 8 R/W-0 R/W-0 U-0 TSYNC TCS — bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 123
... Timer2 clock and gate inputs are used for the 32-bit timer modules, but an interrupt is gener- ated with the Timer3 interrupt flags. © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 11.1 32-bit Operation To configure the Timer2/3 feature for 32-bit operation: 1 ...
Page 124
... T2CON register. 2: The ADC event trigger is available only on Timer2/3. DS70264B-page 122 (1) 1x Gate Sync PR2 PR3 Comparator LSb TMR3 TMR2 TMR3HLD 16 Preliminary TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 TGATE TCS Sync © 2007 Microchip Technology Inc. ...
Page 125
... FIGURE 11-2: TIMER2 (16-BIT) BLOCK DIAGRAM T2CK TGATE 1 Set T2IF 0 Reset Equal © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 1x Gate Sync TMR2 Sync Comparator PR2 Preliminary TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 TCS TGATE DS70264B-page 123 ...
Page 126
... In 32-bit mode, T3CON control bits do not affect 32-bit timer operation. DS70264B-page 124 U-0 U-0 — — R/W-0 R/W-0 (1) TCKPS<1:0> T32 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) ) Preliminary U-0 U-0 U-0 — — — bit 8 U-0 R/W-0 U-0 — TCS — bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 127
... External clock from pin T3CK (on the rising edge Internal clock (F CY bit 0 Unimplemented: Read as ‘0’ Note 1: When 32-bit operation is enabled (T2CON<3> = 1), these bits have no effect on Timer3 operation; all timer functions are set through T2CON. © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 U-0 U-0 (1) — — R/W-0 ...
Page 128
... NOTES: DS70264B-page 126 Preliminary © 2007 Microchip Technology Inc. ...
Page 129
... Mode Select ICOV, ICBNE (ICxCON<4:3>) ICxCON System Bus Note: An ‘x’ signal, register or bit name denotes the number of the capture channel. © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 • Capture timer value on every edge (rising and falling) • Prescaler Capture Event modes: ...
Page 130
... DS70264B-page 128 U-0 U-0 U-0 — — — R-0, HC R-0, HC R/W-0 ICOV ICBNE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary U-0 U-0 — — bit 8 R/W-0 R/W-0 ICM<2:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 131
... OCxIF interrupt flag bit is set. This will result in an interrupt enabled by setting the OCxIE bit. For further information on peripheral interrupts, refer to Section 6.0 “Interrupt Controller”. © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 8. To initiate another single pulse output, change the Timer and Compare register settings, if needed, and then issue a write to set the OCM bits to ‘ ...
Page 132
... See Example 13-1 for PWM mode timing details. Table 13-1 shows example PWM frequencies and resolutions for a device operating at 10 MIPS log 10 F PWM bits log (2) 10 Preliminary © 2007 Microchip Technology Inc. • (Timer Prescale Value) CY ...
Page 133
... FFFFh Resolution (bits) 16 TABLE 13-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MIPS (F PWM Frequency 76 Hz Timer Prescaler Ratio 8 Period Register Value FFFFh Resolution (bits) 16 © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 • (Timer2 Prescale Value) /F )/log 2) bits PWM 10 2) bits 122 Hz 977 Hz ...
Page 134
... OCFA pin controls OC1-OC2 channels. 3: TMR2/TMR3 can be selected via OCTSEL(OCxOCN<3>) bit. DS70264B-page 132 Set Flag bit (1) OCxIF S Q Output Logic R Output Enable 3 OCM2:OCM0 Mode Select 0 1 Period match signals (3) from time bases Preliminary (1) OCx (2) OCFA © 2007 Microchip Technology Inc. ...
Page 135
... Initialize OCx pin low, generate single output pulse on OCx pin 011 = Compare event toggles OCx pin 010 = Initialize OCx pin high, compare event forces OCx pin low 001 = Initialize OCx pin low, compare event forces OCx pin high 000 = Output compare channel is disabled © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 U-0 U-0 U-0 — ...
Page 136
... NOTES: DS70264B-page 134 Preliminary © 2007 Microchip Technology Inc. ...
Page 137
... The module will not respond to SCL transitions while SPIROV is ‘1’, effectively disabling the module until SPIxBUF is read by user software. © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 14.3 Transmit Operations Transmit writes are also double-buffered. The user application writes to SPIxBUF ...
Page 138
... Control Control Clock SDOx bit 0 SDIx SPIxSR Transfer SPIxRXB SPIxBUF Read SPIxBUF DS70264B-page 136 1:1 to 1:8 Secondary Prescaler Select Edge Shift Control Transfer SPIxTXB Write SPIxBUF 16 Internal Data Bus Preliminary 1:1/4/16/64 Primary F CY Prescaler SPIxCON1<1:0> SPIxCON1<4:2> Enable Master Clock © 2007 Microchip Technology Inc. ...
Page 139
... User application must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory mapped to SPIxBUF. FIGURE 14-3: SPI MASTER, FRAME MASTER CONNECTION DIAGRAM dsPIC33F FIGURE 14-4: SPI MASTER, FRAME SLAVE CONNECTION DIAGRAM dsPIC33F © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 PROCESSOR 2 (SPI Slave) SDOx SDIx Serial Receive Buffer SDIx SDOx ...
Page 140
... Invalid 10000 4:1 10000 5000 16:1 2500 1250 64:1 625 312.5 156.25 1:1 5000 2500 4:1 1250 625 16:1 313 156 64 Preliminary 4:1 6:1 8:1 6666.67 5000 2500 1666.67 1250 625 416.67 312.50 104.17 78.125 1250 833 625 313 208 156 © 2007 Microchip Technology Inc. ...
Page 141
... SPIRBF: SPIx Receive Buffer Full Status bit 1 = Receive complete, SPIxRXB is full 0 = Receive is not complete, SPIxRXB is empty Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 U-0 U-0 U-0 — ...
Page 142
... The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). DS70264B-page 140 R/W-0 R/W-0 R/W-0 DISSCK DISSDO MODE16 R/W-0 R/W-0 R/W-0 SPRE<2:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 (1) SMP CKE bit 8 R/W-0 R/W-0 PPRE<1:0> bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 143
... PPRE<1:0>: Primary Prescale bits (Master mode Primary prescale 1 Primary prescale 4 Primary prescale 16 Primary prescale 64:1 Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 Preliminary DS70264B-page 141 ...
Page 144
... Unimplemented: This bit must not be set to ‘1’ by the user application. DS70264B-page 142 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary © 2007 Microchip Technology Inc. U-0 U-0 — — bit 8 R/W-0 U-0 FRMDLY — bit Bit is unknown ...
Page 145
... C master operation with 7 or 10-bit address For details about the communication sequence in each of these modes, refer to the “dsPIC33F Family Refer- ence Manual”. Please see the Microchip web site (www.microchip.com) for the latest dsPIC33F Family Reference Manual sections. © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 2 15 Registers I2CxCON and I2CxSTAT are control and status registers, respectively ...
Page 146
... Start and Stop Bit Generation Collision Detect Acknowledge Generation Clock Stretching I2CxTRN LSb Reload Control Preliminary Internal Data Bus Read Write I2CxMSK Read Write Read Write I2CxSTAT Read Write I2CxCON Read Write Read Write I2CxBRG Read © 2007 Microchip Technology Inc. ...
Page 147
... The control bit IPMIEN enables the module to support the Intelligent Peripheral Management Interface (IPMI). When this bit is set, the module accepts and acts upon all addresses. © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 15.8 General Call Address Support The general call address can address all devices. ...
Page 148
... When the ACTI2C bit in the FPOR configura- tion register is set to ‘1‘, the module uses the SDAx/ SCLx pins. If the ALTI2C bit is ‘0‘, the module uses the ASDAx/ASCLx pins. Preliminary © 2007 Microchip Technology Inc port to its Idle state. ...
Page 149
... General call address disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I Used in conjunction with SCLREL bit Enable software or receive clock stretching 0 = Disable software or receive clock stretching © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 R/W-1 HC R/W-0 R/W-0 SCLREL IPMIEN ...
Page 150
... Start condition not in progress DS70264B-page 148 2 C master, applicable during master receive) C master, applicable during master receive master Hardware clear at end of eighth bit of master receive data byte 2 C master master) Preliminary 2 C master) © 2007 Microchip Technology Inc. ...
Page 151
... Hardware clear at device address match. Hardware set by reception of slave byte. bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 U-0 U-0 R/C-0 HS — ...
Page 152
... I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. DS70264B-page 150 2 C slave device address byte. Preliminary © 2007 Microchip Technology Inc. ...
Page 153
... Unimplemented: Read as ‘0’ bit 9-0 AMSKx: Mask for Address bit x Select bit 1 = Enable masking for bit x of incoming message address; bit match not required in this position 0 = Disable masking for bit x; bit match required in this position © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 U-0 U-0 U-0 — ...
Page 154
... NOTES: DS70264B-page 152 Preliminary © 2007 Microchip Technology Inc. ...
Page 155
... FIGURE 16-1: UART SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator Hardware Flow Control UART Receiver UART Transmitter © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 • Hardware Flow Control Option with UxCTS and UxRTS pins • Fully Integrated Baud Rate Generator with 16-bit prescaler • Baud rates ranging from 1 Mbps to 15 Mbps at 16 MIPS • ...
Page 156
... Desired Baud Rate Preliminary UART BAUD RATE WITH BRGH = Baud Rate = 4 • (BRGx + BRGx = – • Baud Rate denotes the instruction cycle clock /2). OSC CY © 2007 Microchip Technology Inc. /4 ...
Page 157
... Write 0x55 to UxTXREG, which loads the Sync character into the transmit FIFO. After the Break has been sent, the UTXBRK bit is reset by hardware. The Sync character now transmits. © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 16.5 Receiving in 8-bit or 9-bit Data Mode 1. Set up the UART (as described in Section 16.2 “ ...
Page 158
... This feature is only available for the 16x BRG mode (BRGH = 0). DS70264B-page 156 MODE REGISTER x R/W-0 R/W-0 U-0 (1) IREN RTSMD — R/W-0 R/W-0 R/W-0 URXINV BRGH U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R/W-0 UEN<1:0> bit 8 R/W-0 R/W-0 PDSEL<1:0> STSEL bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 159
... STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit Note 1: This feature is only available for the 16x BRG mode (BRGH = 0). © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 MODE REGISTER (CONTINUED) x Preliminary DS70264B-page 157 ...
Page 160
... Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled (IREN = 1). DS70264B-page 158 STATUS AND CONTROL REGISTER x U-0 R/W-0 HC — UTXBRK UTXEN R-1 R-0 RIDLE PERR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared (1) Preliminary R/W-0 R-0 R-1 UTXBF TRMT bit 8 R-0 R/C-0 R-0 FERR OERR URXDA bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 161
... Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Note 1: Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled (IREN = 1). © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 STATUS AND CONTROL REGISTER (CONTINUED) x Preliminary ...
Page 162
... NOTES: DS70264B-page 160 Preliminary © 2007 Microchip Technology Inc. ...
Page 163
... There is only 1 sample-and-hold amplifier in the 12-bit configuration, so simultaneous sampling of multiple channels is not supported. © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 Depending on the particular device pinout, the ADC can have analog input pins, designated AN0 through AN9. In addition, there are two analog input pins for external voltage reference connections ...
Page 164
... AN6 through AN9 are not applicable to dsPIC33FJ12GP201 devices. DS70264B-page 162 (2) CH1 ADC1 S/H (3) - (3) - Conversion Result + (2) CH2 S/H ( (2) CH3 S/H (3) CH1,CH2, - CH3,CH0 - Sample Input Switches + CH0 - S/H - Preliminary Conversion Logic 16-bit ADC Output Buffer Sample/Sequence Control Input MUX Control © 2007 Microchip Technology Inc. ...
Page 165
... REFL FIGURE 17-3: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM ADC Internal RC Clock T CY OSC ( Note: Refer to Figure 7-2 for the derivation the clock frequency. T OSC © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 (ADCS + – 1 ADCS = – V 512 * (V – ...
Page 166
... OUT = sddd dddd dddd 0000, where s = .NOT.d<11>) OUT = dddd dddd dddd 0000) = ssss sddd dddd dddd, where s = .NOT.d<11>) OUT Preliminary R/W-0 R/W-0 R/W-0 AD12B FORM<1:0> bit 8 R/W-0 R/W-0 R/C-0 HC,HS HC, HS ASAM SAMP DONE bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 167
... Automatically set by hardware when ADC conversion is complete. Software can write ‘0’ to clear DONE status (software not allowed to write ‘1’). Clearing this bit will NOT affect any operation in progress. Automatically cleared by hardware at start of a new conversion. © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 Preliminary ...
Page 168
... Always uses channel input selects for Sample A DS70264B-page 166 U-0 U-0 — — R/W-0 R/W-0 SMPI<3:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ADREF- A VSS + A VSS External V - REF + External V - REF Avss Preliminary R/W-0 R/W-0 R/W-0 CSCNA CHPS<1:0> bit 8 R/W-0 R/W-0 R/W-0 BUFM ALTS bit Bit is unknown © 2007 Microchip Technology Inc. ...
Page 169
... T CY • • • 000010 = T · (ADCS<7:0> · 000001 = T · (ADCS<7:0> · 000000 = T · (ADCS<7:0> · © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 R/W-0 R/W-0 R/W-0 SAMC<4:0> R/W-0 R/W-0 R/W-0 ADCS<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared = T CY ...
Page 170
... Reserved 00 = Reserved If AD12B = Reserved 10 = Reserved 01 = CH1, CH2, CH3 negative input CH1, CH2, CH3 negative input is V dsPIC33FJ12GP202 devices only: If AD12B = Reserved 10 = Reserved 01 = Reserved 00 = Reserved If AD12B = CH1 negative input is AN9, CH2 and CH3 negative inputs are not connected ...
Page 171
... Reserved 00 = Reserved If AD12B = Reserved 10 = Reserved 01 = CH1, CH2, CH3 negative input CH1, CH2, CH3 negative input is V dsPIC33FJ12GP202 devices only: If AD12B = Reserved 10 = Reserved 01 = Reserved 00 = Reserved If AD12B = CH1 negative input is AN9, CH2 and CH3 negative inputs are not connected ...
Page 172
... Channel 0 positive input is AN5 • • • 00010 = Channel 0 positive input is AN2 00001 = Channel 0 positive input is AN1 00000 = Channel 0 positive input is AN0 dsPIC33FJ12GP202 devices only: 01001 = Channel 0 positive input is AN9 • • • 00010 = Channel 0 positive input is AN2 00001 = Channel 0 positive input is AN1 ...
Page 173
... Skip ANx for input scan Note 1: On devices without nine analog inputs, all PCFG bits are R/W. However, PCFG bits are ignored on ports without a corresponding input on device. 2: dsPIC33FJ12GP201 devices support only six channels (CSS0-CSS5). © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 U-0 U-0 U-0 — — ...
Page 174
... NOTES: DS70264B-page 172 Preliminary © 2007 Microchip Technology Inc. ...
Page 175
... FUID2 0xF80016 FUID3 Note 1: These reserved bits read as ‘1’ and must be programmed as ‘1’. © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 18.1 Configuration Bits The Configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’), to select various device configurations. These bits are mapped starting at program memory location 0xF80000 ...
Page 176
... OSC2 Pin Function bit (except in XT and HS modes OSC2 is clock output 0 = OSC2 is general purpose digital I/O pin Primary Oscillator Mode Select bits 11 = Primary oscillator disabled Crystal Oscillator mode Crystal Oscillator mode (External Clock) mode Preliminary © 2007 Microchip Technology Inc. ...
Page 177
... WDTPOST<3:0> FWDT ALTI2C FPOR FPWRT<2:0> FPOR © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 Description Watchdog Timer Enable bit 1 = Watchdog Timer always enabled (LPRC oscillator cannot be disabled. Clearing the SWDTEN bit in the RCON register will have no effect Watchdog Timer enabled/disabled by user software (LPRC can be ...
Page 178
... The BOR Status bit (RCON<1>) is set to indicate that a BOR has occurred. The BOR circuit, if enabled, contin- ues to operate while in Sleep or Idle modes and resets the device should VDD fall below the BOR threshold voltage. . Preliminary . The main purpose of the BOR DDCORE © 2007 Microchip Technology Inc. ...
Page 179
... CLRWDT Instruction SWDTEN FWDTEN LPRC Clock (divide by N1) WINDIS © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 18.4.2 SLEEP AND IDLE MODES If the WDT is enabled, it will continue to run during Sleep or Idle modes. When the WDT time-out occurs, the device will wake the device and code execution will continue from where the PWRSAV instruction was executed ...
Page 180
... GS = 3584 IW 001FFEh 000000h VS = 256 IW 0001FEh 000200h 0003FEh BS = 768 IW 000400h 0007FEh 000800h 000FFEh 001000h GS = 3072 IW 001FFEh 000000h VS = 256 IW 0001FEh 000200h 0003FEh BS = 1792 IW 000400h 0007FEh 000800h 000FFEh 001000h GS = 2048 IW 001FFEh “CodeGuard™ © 2007 Microchip Technology Inc. ...
Page 181
... The file register specified by the value ‘f’ • The destination, which could be either the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 Most bit-oriented instructions (including simple rotate/ shift instructions) have two operands: • ...
Page 182
... Moreover, double-word moves require two cycles. Note: For more details on the instruction set, refer to the “dsPIC30F/33F Programmer’s Reference Manual” (DS70157). Description Preliminary © 2007 Microchip Technology Inc. ...
Page 183
... Y data space prefetch address register for DSP instructions ∈ {[W10 [W10 [W10 [W10], [W10 [W10 [W10 [W11 [W11 [W11 [W11], [W11 [W11 [W11 [W11 + W12], none} Y data space prefetch destination register for DSP instructions ∈ {W4..W7} Wyd © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 Description Preliminary DS70264B-page 181 ...
Page 184
... Branch if Accumulator B overflow Branch if Overflow Branch if Accumulator A saturated Branch if Accumulator B saturated Branch Unconditionally Branch if Zero Computed Branch Bit Set f Bit Set Ws Write C bit to Ws<Wb> Write Z bit to Ws<Wb> Bit Toggle f Bit Toggle Ws Preliminary © 2007 Microchip Technology Inc Status Flags Words Cycles Affected 1 1 OA,OB,SA, C,DC,N,OV,Z 1 ...
Page 185
... DEC2 DEC2 f DEC2 f,WREG DEC2 Ws,Wd 28 DISI DISI #lit14 © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 Description Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Bit Test Bit Test Ws<Wb> Bit Test Ws< ...
Page 186
... Move f to WREG Move 16-bit literal to Wn Move 8-bit literal to Wn Move Move Move WREG to f Move Double from W(ns):W( Move Double from Ws to W(nd + 1):W(nd) Prefetch and store accumulator Preliminary © 2007 Microchip Technology Inc Status Flags Words Cycles Affected 1 18 N,Z,C,OV ...
Page 187
... RLNC Ws,Wd 65 RRC RRC f RRC f,WREG RRC Ws,Wd © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 Description Multiply Accumulator Square Wm to Accumulator -(Multiply Wm by Wn) to Accumulator Multiply and Subtract from Accumulator {Wnd + 1, Wnd} = signed(Wb) * signed(Ws) {Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws) {Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws) ...
Page 188
... Read Prog<23:16> to Wd<7:0> Read Prog<15:0> Write Ws<7:0> to Prog<23:16> Write Ws to Prog<15:0> Unlink Frame Pointer .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR .XOR .XOR. lit5 Wnd = Zero-extend Ws Preliminary © 2007 Microchip Technology Inc Status Flags Words Cycles Affected ...
Page 189
... Plus Development Programmer - MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2007 Microchip Technology Inc. 20.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...
Page 190
... MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. Preliminary ® DSCs on an instruction © 2007 Microchip Technology Inc. ...
Page 191
... Microchip Technology Inc. 20.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, ...
Page 192
... Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) and the latest “Product Selector Guide” (DS00148) for the complete list of demonstration, development and evaluation kits. Preliminary © 2007 Microchip Technology Inc. ® L security ICs, CAN ® ...
Page 193
... Maximum allowable current is a function of device maximum power dissipation (see Table 21-2). 3: Exceptions are CLKOUT, which is able to sink/source 25 mA, and the V and PGDx pins, which are able to sink/source 12 mA. © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 .................................................................................. -0.3V to +5.6V SS ...
Page 194
... Max Unit -40 — +125 °C -40 — +85 °C -40 — +140 °C -40 — +125 ° INT – T )/θ Typ Max Unit Notes 66 — °C — °C/W 1 63.6 — °C/W 1 80.2 — °C — °C/W 1 © 2007 Microchip Technology Inc. ...
Page 195
... Internal regulator voltage Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 2: This is the limit to which These parameters are characterized but not tested in manufacturing. © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature (1) Min Typ Max 3 ...
Page 196
... OSC1 DD Preliminary 3.3V 10 MIPS 3.3V 16 MIPS 3.3V 20 MIPS 3.3V 30 MIPS 3.3V 40 MIPS 3.3V 35 MIPS . SS © 2007 Microchip Technology Inc. ...
Page 197
... Base I current is measured with core off, clock on and all modules turned off. Peripheral Module IDLE Disable SFR registers are zeroed. All I/O pins are configured as inputs and pulled to V © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 ) IDLE Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) -40° ...
Page 198
... Preliminary ) PD (3,4) Base Power-Down Current (3) Watchdog Timer Current: ΔI WDT ≤ +85°C for Industrial A ≤ +125°C for Extended A Conditions 3.3V 40 MIPS 3.3V 40 MIPS 3.3V 40 MIPS 3.3V 35 MIPS © 2007 Microchip Technology Inc. ...
Page 199
... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. © 2007 Microchip Technology Inc. dsPIC33FJ12GP201/202 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) -40°C ≤ T Operating temperature -40° ...
Page 200
... Preliminary ≤ +85°C for Industrial A ≤ +125°C for Extended A Units Conditions 2mA 3. 2mA 3. -2 -1 ≤ +85°C for Industrial A ≤ +125°C for Extended A Max Units Conditions 2.55 V © 2007 Microchip Technology Inc. ...