DSPIC30F4012 Microchip Technology Inc., DSPIC30F4012 Datasheet - Page 153

• Manufacturer Part Number: DSPIC30F4012
• Description: Dspic30f4011/4012 Enhanced Flash 16-bit Digital Signal Controller
• Manufacturer: Microchip Technology Inc.

21.3
The dsPIC30F4011/4012 devices differentiate between
various kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
FIGURE 21-2:
21.3.1
A power-on event generates an internal POR pulse
when a V
the POR circuit threshold voltage (V
inally 1.85V. The device supply voltage characteristics
must meet specified starting voltage and rise rate
requirements. The POR pulse resets a POR timer and
places the device in the Reset state. The POR also
selects the device clock source identified by the
oscillator Configuration fuses.
© 2007 Microchip Technology Inc.
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during Sleep
Watchdog Timer (WDT) Reset (during normal
operation)
Programmable Brown-out Reset (BOR)
RESET Instruction
Reset caused by trap lock-up (TRAPR)
Reset caused by illegal opcode, or by using an
uninitialized W register as an Address Pointer
(IOPUWR)
MCLR
V
Illegal Opcode/
Uninitialized W Register
DD
Reset
DD
Instruction
POR: POWER-ON RESET
RESET
rise is detected. The Reset pulse occurs at
Trap Conflict
Brown-out
V
Sleep or Idle
Module
Detect
DD
WDT
Reset
RESET SYSTEM BLOCK DIAGRAM
Rise
BOREN
Glitch Filter
Digital
POR
POR
) which is nom-
BOR
Different registers are affected in different ways by
various Reset conditions. Most registers are not
affected by a WDT wake-up, since this is viewed as the
resumption of normal operation. Status bits from the
RCON register are set or cleared differently in different
Reset situations, as indicated in Table 21-5. These bits
are used in software to determine the nature of the
Reset.
A block diagram of the on-chip Reset circuit is shown in
Figure 21-2.
A MCLR noise filter is provided in the MCLR Reset
path. The filter detects and ignores small pulses.
Internally generated Resets do not drive MCLR pin low.
The POR circuit inserts a small delay, T
nominally 10 μs and ensures that the device bias
circuits are stable. Furthermore, a user-selected
power-up time-out (T
parameter is based on device Configuration bits and
can be 0 ms (no delay), 4 ms, 16 ms or 64 ms. The total
delay is at device power-up, T
these delays have expired, SYSRST will be negated on
the next leading edge of the Q1 clock and the PC jumps
to the Reset vector.
The timing for the SYSRST signal is shown in
Figure 21-3 through Figure 21-5.
dsPIC30F4011/4012
S
R
PWRT
) is applied. The T
Q
POR
DS70135E-page 151
+ T
POR
SYSRST
PWRT
, which is
. When
PWRT