DSPIC33FJ64GS406 Microchip Technology Inc., DSPIC33FJ64GS406 Datasheet - Page 4
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DSPIC33FJ64GS406
Manufacturer Part Number
DSPIC33FJ64GS406
Description
High-performance, 16-bit Digital Signal Controllers
Manufacturer
Microchip Technology Inc.
Datasheet
1.DSPIC33FJ64GS406.pdf
(418 pages)
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dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610
Peripheral Features (Continued)
• UART (up to two modules):
• Enhanced CAN (ECAN™ module) 2.0B active:
• Quadrature Encoder Interface (up to 2 modules):
High-Speed PWM Module Features:
• Up to nine PWM generators with up to 18 outputs
• Primary and Secondary time-base
• Individual time base and duty cycle for each of the
• Dead time for rising and falling edges:
• Phase shift resolution of 1.04 ns
• Frequency resolution of 1.04 ns
• PWM modes supported:
DS70591C-page 4
- Interrupt on address bit detect
- Interrupt on UART error
- Wake-up on Start bit from Sleep mode
- 4-character TX and RX FIFO buffers
- LIN bus support
- IrDA
- High-Speed Baud mode
- Hardware Flow Control with CTS and RTS
- Up to eight transmit and up to 32 receive buffers
- 16 receive filters and three masks
- Loopback, Listen Only and Listen All
- Messages modes for diagnostics and bus
- Wake-up on CAN message
- Automatic processing of Remote
- FIFO mode using DMA
- DeviceNet™ addressing support
- Phase A, Phase B, and index pulse input
- 16-bit up/down position counter
- Count direction status
- Position Measurement (x2 and x4) mode
- Programmable digital noise filters on inputs
- Alternate 16-bit Timer/Counter mode
- Interrupt on position counter rollover/underflow
PWM output
- Duty cycle resolution of 1.04 ns
- Dead-time resolution of 1.04 ns
- Standard Edge-Aligned
- True Independent Output
- Complementary
- Center-Aligned
- Push-Pull
- Multi-Phase
- Variable Phase
- Fixed Off-Time
- Current Reset
- Current-Limit
monitoring
Transmission Requests
©
encoding and decoding in hardware
Preliminary
• Independent Fault/Current-Limit inputs
• Output override control
• Special Event Trigger
• PWM capture feature
• Prescaler for input clock
• Dual Trigger from PWM TO ADC
• PWMxL, PWMxH output pin swapping
• On-the-Fly PWM Frequency, Duty cycle and
• Disabling of Individual PWM generators
• Leading-Edge Blanking (LEB) functionality
High-Speed Analog Comparator:
• Up to four Analog Comparators:
• PWM module interface:
Interrupt Controller:
• 5-cycle latency
• Up to five external interrupts
• Seven programmable priority levels
• Five processor exceptions
High-Speed 10-bit ADC:
• 10-bit resolution
• Up to 24 input channels grouped into 12
• Two internal reference monitoring inputs grouped
• Successive Approximation Register (SAR)
• Dedicated result buffer for each analog channel
• Independent trigger source section for each
Power Management:
• On-chip 2.5V voltage regulator
• Switch between clock sources in real time
• Idle, Sleep, and Doze modes with fast wake-up
Phase Shift changes
- 20 ns response time
- 10-bit DAC for each analog comparator
- DACOUT pin to provide DAC output
- Programmable output polarity
- Selectable input source
- ADC sample and convert capability
- PWM Duty Cycle Control
- PWM Period Control
- PWM Fault Detect
conversion pairs
into a pair
converters for parallel conversions of analog pairs:
- 4 Msps for devices with two SARs
- 2 Msps for devices with one SAR
analog input conversion pairs
2010 Microchip Technology Inc.
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