A2550 Allegro MicroSystems, Inc., A2550 Datasheet
A2550
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A2550 Summary of contents
Page 1
... The ® Allegro A2550 combines the functions of voltage regulator, watchdog, and reset, as well as three low-side DMOS relay driver outputs. Primarily targeted at automotive applications, this IC is designed to provide robust performance over extended voltage and temperature ranges ...
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... A2550 Description (continued) The A2550 also includes power-on reset circuitry (NPOR) as well as an integrated watchdog circuit. Combined, they service the monitoring and reset requirements of a system microprocessor. The A2550 is supplied in a 16-pin TSSOP package with exposed thermal pad (package LP).The package is lead (Pb) free, with 100% matte tin leadframe plating ...
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... Fault Logic A LGND and PGND must be connected externally. Suitable Characteristics 33 μ electrolytic United Chemi-Con EGXE630E--330MH12D 0.47 μ X7R ceramic 0.22 μ X7R ceramic for Automotive Applications VBAT A2550 Internal V ref Reference CPOR Adjustable Delay Relays or Other Inductive Loads Vdc ...
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... A2550 ELECTRICAL CHARACTERISTICS, –40°C ≤ T Characteristics Supply VBB Operating Voltage 1 VBB Supply Current Logic Inputs ENBAT Input Voltage 2 EN, WDI, and INx Input Voltage ENBAT, EN, WDI, INx Input Voltage Hysteresis ENBAT Input Current 2,3 EN Input Current 2 WDI Input Current 2 INx Input Current ...
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... A2550 ELECTRICAL CHARACTERISTICS, continued –40°C ≤ T Characteristics Watchdog and Power-On Reset NPOR Active Voltage NPOR Inactive Leakage Current CWD and CPOR Trip Voltage CPOR Charge Current 5 Power-On Reset Cycle Time CWD Charge Current Thermal Protection Thermal Shut Down Threshold Thermal Shut Down Hysteresis ...
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... A2550 0.01 Figure 1. Dynamic thermal impedance of an individual output stage during active clamp of an inductive load (mounted on a 4-layer PCB based on JEDEC standard). Nonrepetitive Output Active Clamp Power Dissipation 100 10 1 0.01 Figure 2. Peak power dissipation curves for nonrepetitive clamped outputs. Output voltage is clamped during turn-off of inductive loads while current decays ...
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... A2550 Pin Descriptions EN Enable pin; logical OR with ENBAT. This logic-level input enables the A2550. If there are no faults, the regulator is live and outputs can be switched. When both the EN and ENBAT pins are held low, the A2550 enters Sleep mode. ENBAT Enable pin; logical OR with EN. Same as EN, ...
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... A2550 Timing Diagram: Initial Start-up and Exiting Sleep Mode VBB VREG5 WDI CWD EN or ENBAT CPOR NPOR OUTx Relay Driver with 5 V Regulator Internal V ref t POR Internal V ref ~INx signal to wake up microcontroller. OUTx enabled with first watchdog pulse. ...
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... A2550 VREG5 WDI CWD CPOR NPOR OUTx outputs enabled Relay Driver with 5 V Regulator Timing Diagram: Watchdog Monitoring WDR Missing watchdog detected (WDI low). NPOR pulses generated periodically. NPOR inactive, but outputs not enabled until watchdog detected. ...
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... A2550 Timing Diagram: VREG5 UVLO and TSD Monitoring VBB VREG5 WDI CWD Internal VREG5 UVLO CPOR NPOR Internal TSD OUTx Relay Driver with 5 V Regulator outputs enabled ~INx VREG5 undervoltage detected. VREG5 recovers, and after it rises above V UVLO flag is deactivated and CPOR recharges ...
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... Fault Logic The A2550 offers several protection and fault detection features. The operation of thermal shutdown, watchdog monitoring of the microcontroller, and regulated voltage undervoltage lockout are described in the Timing Diagrams section. The fault logic is described in table 1. ...
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... INx is reapplied. V (3) Sleep TRIP(L) The A2550 is put to sleep by holding both EN and ENBAT low. In sleep mode all functions are shut down, including VREG5. If the VREG5 regulator is required at all times, dis- able sleep mode by tying ENBAT to VBB. Power Limits ...
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... A2550 × DS(on) LS1 DS(on × DS(on) LS3 Because 110 mA , and LS1 LS2 LS3 given that Ω, then DS(on Ω) * (110 mA 182 Given also BIAS REG mW+ 182 mW+ 182 mW = 406 can be calculated by substitution into equation 6: ...
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... A2550 A more rigorous derivation, including R exponential current decay results in ⎡ ⎢ ⎢ ⎣ COIL COIL and L t COIL ln – COIL Energy loss in the driver is COIL COIL Terminal List Table No ...
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... A2550 5. 3.00 16X 0.10 C 0.25 0.65 Copyright ©2006, 2007, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products ...