EM65571 ELAN Microelectronics Corp, EM65571 Datasheet - Page 74

• Manufacturer Part Number: EM65571
• Description: 130com / 128seg 65k Color Stn Lcd Driver
• Manufacturer: ELAN Microelectronics Corp

EM65571
130COM/128SEG 65K Color STN LCD Driver
Control Register Table (Bank 5)
Note: The asterisk “*” mark means “don’t care”
68 x
Window X End Address
(Lower nibble)
Window X End Address
(Upper nibble)
Window Y End Address
(Lower nibble)
Window Y End Address
(Upper nibble)
Start Address for line
reverse (Lower nibble)
Start Address for line
reverse (Upper nibble)
End Address for line
reverse (Lower nibble)
End Address for line
reverse (Upper nibble)
Line reverse control
Burst RAM write control
Reverse type
Regulator multiple ratio
Control Register
EEPROM mode select
register
Vop calibration offset
register
Register Access Control
Parentheses [ ] shows the control register address.
Address [CH], [DH], [EH] in Bank 5 of the control register are reserved.
Control Register
8.2 Control Register Functions
The EM65571 has many control registers. In case of control register access, the upper
nibble of the data bus (D7~D4) represents the register address, the lower nibble of the
data bus (D3~D0) represents the data. The access example is shown in the following.
The Pins (CSB, RS, RDB, WRB) setting is for the 80-family MPU interface. Only the
setting of the terminal (RDB, WRB) is different, when it is accessed by the 68-family
MPU.
Example: X Address
In writing to the control register, direct addressing to D7~D4 of the data bus can be
used. In case of a register read, first set the RA register for a specific register address,
next read that specific register. Therefore, two steps are needed to perform a register
read. Then, specific register output to D3~D0 of the data bus. Except for D3~D0 of the
data bus, all are “H”. Access to undefined register address area is not allowed. When
RS is “L”, all read/write operations are accessible in the display RAM. The data bus
does not include the register address. In case of a write operation, D3~D0 data is
written to the register designated at D7~D4 at the rising edge of the WRB signal. In
[0H]
[1H]
[2H]
[3H]
[4H]
[5H]
[6H]
[7H]
[8H]
[9H]
[AH]
[BH]
[FH]
D7
0
Register address
CSB RS WRB RDB RE2 RE1 RE0 D7 D6 D5 D4 D3
D6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pins (for 80-family) & Bank
1
1
1
1
1
1
1
1
1
1
1
1
1
D5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
D4
0
1
1
1
1
1
1
1
1
1
1
1
1
1 0/1
AX3 AX2 AX1 AX0
D3
1
1
1
1
1
1
1
1
1
1
1
1
0/1
0
0
0
0
0
0
0
0
0
0
0
0
D2
0/1
Data
1
1
1
1
1
1
1
1
1
1
1
1
D1
0
0
0
0
0
0
0
0
1
1
1
1
1
(This specification is subject to change without further notice)
0
0
0
0
1
1
1
1
0
0
0
0
1
D0
0
0
1
1
0
0
1
1
0
0
1
1
1
Address & Code
0 EX3 EX2 EX1 EX0
1 EX7 EX6 EX5 EX4
0 EY3 EY2 EY1 EY0
1 EY7 EY6 EY5 EY4
0 LS3 LS2 LS1 LS0
1 LS7 LS6 LS5 LS4
0 LE3 LE2 LE1 LE0
1 LE7 LE6 LE5 LE4
0 *
1 *
0 M1
1 CV4 CV3 CV2 CV1 set Vop offset voltage
1 T0
TS
CSB
0
Product Specification (V1.0) 08.04.2005
D2
BST BT
RM2 RM1 RM0 set regulator multiple ratio
M0
RE2 RE1 RE0 RE:set register bank number
Pins setting
RS
1
D1
EXT OSC OSC:oscillator frequency select
VPP_
D0
LR
EV
RDB
1
Set X end address for
window function access
Set X end address for
window function access
Set Y end address for
window function access
Set Y end address for
window function access
Set start line for line reverse display
Set start line for line reverse display
Set end line for line reverse display
Set end line for line reverse display
BST: Burst RAM write ON / OFF
BT: Reverse type select
LREV: Line reverse control
M1,M0:EEPROM mode select
VPP_EXT:EEPROM power select
TST0:for LS1 test,must set to "0"
WRB
0
RE2
0
Function
Register Bank
RE1
0
RE0
0