RTL8169S-32 ETC-unknow, RTL8169S-32 Datasheet - Page 12

• Manufacturer Part Number: RTL8169S-32
• Description: Single-chip Gigabit Nic Ethernet Controller
• Manufacturer: ETC-unknow

5.2. PCI Interface
Integrated Gigabit Ethernet Controller (NIC)
Symbol
PCIADPIN63-32
PCIADPIN31-0
CBEBPIN7-4
CBEBPIN3-0
Type
T/S
T/S
T/S
T/S
97, 98, 102,
33, 34, 36,
37, 39, 40,
42, 43, 47,
49, 50, 53,
55, 57, 58,
59, 79, 82,
83, 85, 86,
87, 89, 90,
93, 95, 96,
44, 60, 77,
(128QFP)
103, 104
Pin No.
92
U8, U9, U11,
M2, M3, N1,
T8, T9, T10,
T3, R4, U4,
T5, T6, U7,
T1, T2, U2,
R3, T4, U3,
R5, U5, T7,
(233BGA)
N16, M17,
M15, K17,
Table 2.
U12, U13,
R12, R15,
U16, U17,
G17, G15,
D17, C17,
T12, U14,
L16, K16,
H16, G16,
C16, A17,
B16, D15,
A15, C14,
U15, T14,
R17, P16,
E17, E15,
J16, H17,
F16, E16,
B13, C12
L17, D16
J17, J15,
T11, R9,
R6, T13,
Pin No.
B17
R1
PCI Interface
Description
AD63-32: High 32-bit PCI address and data multiplexed
pins.
Address and Data are multiplexed on the same pins and
provide 32 additional bits. During an address phase (when
using the DAC command and when REQ64B is asserted),
the upper 32-bits of a 64-bit address are transferred;
otherwise, these bits are reserved but are stable and
undetermined. During a data phase, an additional 32-bits of
data are transferred when a 64-bit transaction has been
negotiated by the assertion of REQ64B and ACK64B.
AD31-0: Low 32-bit PCI address and data multiplexed pins.
The address phase is the first clock cycle in which
FRAMEB is asserted. During the address phase, AD31-0
contains a physical address (32 bits). For I/O, this is a byte
address, and for configuration and memory, it is a
double-word address. The RTL8169S supports both
big-endian and little-endian byte ordering. Write data is
stable and valid when IRDYB is asserted. Read data is
stable and valid when TRDYB is asserted. Data I is
transferred during those clocks where both IRDYB and
TRDYB are asserted.
AD16-0: Boot PROM Address Bus. These pins are used to
access up to a 128k-byte flash memory or EPROM.
AD31-24: Boot PROM data bus during Boot PROM mode.
PCI bus command and byte enables multiplexed pins.
During the address phase of a transaction, CBEBPIN7-4
define the bus command. During the data phase,
CBEBPIN7-4 are used as Byte Enables. The Byte Enables
are valid for the entire data phase and determine which byte
lanes carry meaningful data. CBEBPIN4 applies to byte 4,
and CBEBPIN7 applies to byte 7.
PCI bus command and byte enables multiplexed pins.
During the address phase of a transaction, CBEBPIN3-0
define the bus command. During the data phase,
CBEBPIN3-0 are used as Byte Enables. The Byte Enables
are valid for the entire data phase and determine which byte
lanes carry meaningful data. CBEBPIN0 applies to byte 0,
and CBEBPIN3 applies to byte 3.
6
RTL8169S-32/RTL8169S-64
Track ID: JATR-1076-21
Datasheet
Rev. 1.7