ATF1504ASVL ATMEL Corporation, ATF1504ASVL Datasheet

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... Pull-up Option on JTAG Pins TMS and TDI • Advanced Power Management Features – Edge-controlled Power-down “L” – Individual Macrocell Power Option – Disable ITD on Global Clocks, Inputs and I/O Low-voltage, Complex Programmable Logic Device ATF1504ASV ATF1504ASVL Rev. 1409J–PLD–6/05 1 ...

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TQFP Top View I/O/TDI 1 I/O 2 I/O 3 GND 4 PD1/I/O 5 I/O 6 TMS/I/O 7 I/O 8 VCC 9 I/O 10 I/O 11 68-lead PLCC Top View I/O 10 VCCIO 11 I/O/TD1 12 I/O 13 I/O 14 ...

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PQFP Top View I/O 3 I/O 4 VCCIO 5 I/O/TDI I I/O 10 I/O 11 I/O 12 GND 13 I/O/PD1 14 I/O 15 I/O 16 I/O/TMS 17 I/O 18 ...

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Description ATF1504ASV(L) 4 The ATF1504ASV( high-performance, high-density complex programmable logic device (CPLD) that utilizes Atmel’s proven electrically-erasable memory technology. With 64 logic macrocells and inputs, it easily integrates logic from several TTL, SSI, MSI, LSI ...

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Block Diagram Product Terms and Select Mux 1409J–PLD–6/05 Unused product terms are automatically disabled by the compiler to decrease power consumption. A security fuse, when programmed, protects the contents of the ATF1504ASV(L). Two bytes (16 bits) of User Signature are ...

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OR/XOR/CASCADE Logic Flip-flop Extra Feedback I/O Control Global Bus/Switch Matrix Foldback Bus ATF1504ASV(L) 6 The ATF1504ASV(L)’s logic structure is designed to efficiently support all types of logic. Within a single macrocell, all the product terms can be routed to the ...

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Figure 1. ATF1504ASV(L) Macrocell Programmable Pin-keeper Option for Inputs and I/Os The ATF1504ASV(L) offers the option of programming all input and I/O pins so that pin keeper circuits can be utilized. When any pin is driven high or low and ...

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Input Diagram I/O Diagram Speed/Power Management ATF1504ASV(L) 8 The ATF1504ASV(L) has several built-in speed and power management features. The ATF1504ASV(L) contains circuitry that automatically puts the device into a low power standby mode when no logic transitions are occurring. This ...

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Design Software Support Power-up Reset Security Fuse Usage 1409J–PLD–6/05 All power-down AC characteristic parameters are computed from external input or I/O pins, with reduced-power bit turned on. For macrocells in reduced-power mode (reduced-power bit turned on), the reduced-power adder, t ...

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Programming ISP Programming Protection ATF1504ASV(L) 10 ATF1504ASV(L) devices are in-system programmable (ISP) devices utilizing the 4-pin JTAG protocol. This capability eliminates package handling normally required for pro- gramming and facilitates rapid design iterations and field changes ...

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DC and AC Operating Conditions Operating Temperature (Ambient)) V (3.3V) Power Supply CC DC Characteristics Symbol Parameter Input or I/O Low I IL Leakage Current Input or I/O High I IH Leakage Current Tri-State Output I OZ Off-State Current Power ...

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Absolute Maximum Ratings* Temperature Under Bias.................................. -40°C to +85°C Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground .........................................-2.0V to +7.0V Voltage on Input Pins with Respect to Ground During Programming.....................................-2.0V to +14.0V Programming Voltage ...

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AC Characteristics Symbol Parameter t Input or Feedback to Non-Registered Output PD1 t I/O Input or Feedback to Non-Registered Feedback PD2 t Global Clock Setup Time SU t Global Clock Hold Time H t Global Clock Setup Time of Fast ...

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AC Characteristics (Continued) Symbol Parameter Output Buffer Enable Delay t ZX2 (Slow slew rate = OFF; V Output Buffer Enable Delay t ZX3 (Slow slew rate = ON Output Buffer Disable Delay ( Register Setup Time ...

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Power-down Mode Power Down AC Characteristics Symbol Parameter t Valid I, I/O before PD High IVDH (2) t Valid OE before PD High GVDH (2) t Valid Clock before PD High CVDH t I, I/O Don’t Care after PD High ...

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JTAG-BST/ISP Overview JTAG Boundary-scan Cell (BSC) Testing BSC Configuration for Input and I/O Pins (Except JTAG TAP Pins) ATF1504ASV(L) 16 The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller in the ATF1504ASV(L). The boundary-scan technique involves ...

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BSC Configuration for Macrocell 1409J–PLD–6/05 Pin BSC 0 Pin 1 TDI Shift TDO OEJ OUTJ Capture Update DR DR TDI Clock Shift Macrocell BSC ATF1504ASV(L) TDO D Q ...

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ATF1504ASV Dedicated Pinouts 44-lead Dedicated Pin TQFP INPUT/OE2/GCLK2 40 INPUT/GCLR 39 INPUT/OE1 38 INPUT/GCLK1 37 I/O /GCLK3 35 I (1, I/O / TDI (JTAG) 1 I/O / TMS (JTAG) 7 I/O / TCK (JTAG) 26 I/O ...

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ATF1504ASV I/O Pinouts 44-lead 44-lead 68-lead MC PLC PLCC TQFP PLCC PD1 ...

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SUPPLY CURRENT VS. SUPPLY VOLTAGE (T = 25° 100 75 STANDARD POWER 2.50 2.75 3.00 3.25 SUPPLY VOLTAGE (V) SUPPLY CURRENT VS. SUPPLY VOLTAGE PIN-CONTROLLED POWER-DOWN MODE (T = 25° ...

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OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE (V = 3.3V 25° 100 0.5 1 1.5 2 OUTPUT VOLTAGE (V) INPUT CLAMP CURRENT VS. INPUT VOLTAGE (V = 3.3V 25°C) ...

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... ATF1504ASV-15 JI84 ATF1504ASV-15 QI100 ATF1504ASV-15 AI100 ATF1504ASVL-20 AC44 ATF1504ASVL-20 JC44 (2) ATF1504ASVL-20 JC68 (3) ATF1504ASVL-20 JC84 (2) ATF1504ASVL-20 QC100 ATF1504ASVL-20 AC100 ATF1504ASVL-20 AI44 ATF1504ASVL-20 JI44 ATF1504ASVL-20 JI68 ATF1504ASVL-20 JI84 ATF1504ASVL-20 QI100 ATF1504ASVL-20 AI100 by 15%. CC Package Operation Range 44A 44J 68J Commercial 84J ( ...

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... Body, Thin Profile Plastic Quad Flat Package (TQFP) 1409J–PLD–6/05 Ordering Code ATF1504ASV-15 AU44 ATF1504ASV-15 JU44 ATF1504ASV-15 AU100 ATF1504ASVL-20 AU44 ATF1504ASVL-20 JU44 ATF1504ASVL-20 AU100 Package Type ATF1504ASV(L) Package Operation Range 44A Industrial 44J (- +85 C) 100A ...

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Packaging Information 44A – TQFP PIN 1 PIN 1 IDENTIFIER e C 0˚~7˚ L Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm ...

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PLCC 1.14(0.045) X 45˚ 0.51(0.020)MAX 45˚ MAX (3X) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. ...

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PLCC 1.14(0.045) X 45˚ 0.51(0.020)MAX 45˚ MAX (3X) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AE. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. ...

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PLCC 1.14(0.045) X 45˚ 0.51(0.020)MAX 45˚ MAX (3X) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AF. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. ...

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PQFP PIN 1 ID PIN 0º~7º C 2325 Orchard Parkway San Jose, CA 95131 R ATF1504ASV( TITLE 100Q1, 100-lead Body, 3.2 mm Footprint, ...

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TQFP PIN 0˚~7˚ L Notes: 1. This package conforms to JEDEC reference MS-026, Variation AED. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and ...

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Revision History ATF1504ASV(L) 30 Revision Comments Green package options added. 1409J 1409J–PLD–6/05 ...

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... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © Atmel Corporation 2005. All rights reserved. Atmel marks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Atmel Operations Memory ...