AD5560 Analog Devices, Inc., AD5560 Datasheet - Page 16

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AD5560

Manufacturer Part Number
AD5560
Description
1.2 A Programmable Device Power Supply With Integrated 16-bit Level Setting Dacs
Manufacturer
Analog Devices, Inc.
Datasheet

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AD5560
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Mnemonic
CLALM
KELALM
TMPALM
CPOH/CPO
CPOL
BUSY
SDO
DV
DGND
SCLK
SDI
SYNC
RCLK
RESET
CLEN/LOAD
HW_INH/LOAD
REFGND
CC
NOTES
1. NC = NO CONNECT.
2. EXPOSED PAD ON TOP OF PACKAGE. EXPOSED PAD IS INTERNALLY CONNECTED TO
HW_INH/LOAD
MOST NEGATIVE POINT, AV
CLEN/LOAD
CPOH/CPO
TMPALM
KELALM
CLALM
RESET
DGND
CPOL
BUSY
SYNC
RCLK
Description
Clamp Alarm Output. Open-drain output, active low; this pin can be programmed to be either latched or
unlatched.
Kelvin Alarm Pin for SENSE and DUTGND, Open-Drain Active Low. This pin can be programmed to be either
latched or unlatched.
Temperature Alarm Flag. Open-drain output, active low; this pin can be programmed to be either latched or
unlatched.
Comparator High Output (CPOH) or Window Comparator Output (CPO).
Comparator Low Output.
Open-Drain Active Low Output. This pin indicates the status of the calibration engine for the DAC channels.
Serial Data Output. This pin is used for reading back DAC and DPS register information for diagnostic
purposes.
Digital Supply Voltage.
Digital Ground Reference Point.
Clock Input, Active Falling Edge.
Serial Data Input.
Frame Sync, Active Low.
Ramp Clock Logic Input. If the ramp function is used, a clock signal of 833 kHz maximum should be applied to
this input to drive the ramp circuitry. Tie RCLK low if it is unused.
Logic Input. This pin is used to reset all internal nodes on the device to their power-on reset value.
Clamp Enable. This input allows the user to enable or disable the clamp circuitry. This pin can be configured
as a LOAD function to allow synchronization of multiple devices. Either CLEN or HW_INH can be chosen as
LOAD input (see the system control register, Address 0x1).
Hardware Inhibit Input to Disable Force Amplifier. This pin can be configured as a LOAD function to allow
synchronization of multiple devices. Either CLEN or HW_INH can be chosen as a LOAD input (see the system
control register, Address 0x1).
Accurate Ground Reference for Applied Voltage Reference.
SCLK
DV
SDO
SDI
CC
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
64
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PIN 1
63
62
SS
61
.
60
EXPOSED PAD ON TOP
Figure 6. Pin Configuration
59
Rev. B | Page 16 of 60
(Not to Scale)
58
AD5560
TOP VIEW
57
56
55
54
53
52
51
50
49
48
47
46
44
43
42
40
39
38
37
36
35
34
33
45
41
EXTMEASIH2
EXTMEASIH1
AV
AV
AGND
GUARD/SYS_DUTGND
EXTMEASIL
SENSE
DUTGND
C
C
C
C
C
NC
AV
F0
F1
F2
F3
F4
DD
SS
DD

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