ADN2813 Analog Devices, Inc., ADN2813 Datasheet - Page 11

• Manufacturer Part Number: ADN2813
• Description: Continuous Rate 10 Mb/s To 1.25 Gb/s Clock And Data Recovery Ic With Integrated Limiting Amp
• Manufacturer: Analog Devices, Inc.

Table 6. Internal Register Map
Reg.
Name
FREQ0
FREQ1
FREQ2
RATE
MISC
CTRLA
CTRLB
CTRLC
1
Table 7. Miscellaneous Register, MISC
D7
x
Table 8. Control Register, CTRLA
F
D7
0
0
1
1
1
Table 9. Control Register, CTRLB
Config LOL
D7
0 = LOL pin normal operation
1 = LOL pin is static LOL
Table 10. Control Register, CTRLC
D7
Set to 0
All writeable registers default to 0x00.
Where DIV_F
REF
Range
D6
x
D6
0
1
0
1
R/W
R
R
R
R
R
W
W
W
D6
Set to 0
REF
LOS Status
D5
0 = No loss of signal
1 = Loss of signal
10 MHz to 20 MHz
20 MHz to 40 MHz
40 MHz to 80 MHz
80 MHz to 160 MHz
is the divided down reference referred to the 10 MHz to 20 MHz band (see the Reference Clock (Optional) section).
Address
0x0
0x1
0x2
0x3
0x4
0x8
0x9
0x11
D5
Set to 0
D7
MSB
MSB
0
x
Config.
LOL
0
1
D4
Set to 0
Reset MISC[4]
D6
Write a 1 followed by
0 to reset MISC[4]
1
F
Static LOL
D4
0 = Waiting for next LOL
1 = Static LOL until reset
COARSE_RD[8] MSB
REF
Data Rate/Div_F
D5
0
0
0
1
Range
D6
MSB
x
Reset
MISC[4]
0
D3
Set to 0
D4
0
0
0
0
n
D3
0
0
1
0
D5
LOS
Status
System
Reset
0
REF
Config. LOS
D2
0 = Active high LOS
1 = Active low LOS
D2
0
1
0
0
System Reset
D5
Write a 1 followed by 0
to reset ADN2813
Ratio
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1
2
4
2
256
Data Rate/DIV_F
n
D4
Static
LOL
0
0
LOL Status
D3
0 = Locked
1 = Acquiring
Coarse Data Rate Readback
Measure Data Rate
D1
Set to 1 to measure data rate
D3
LOL
Status
Reset
MISC[2]
0
SQUELCH Mode
D1
0 = SQUELCH CLK and DATA
1 = SQUELCH CLK or DATA
REF
Data Rate Measurement
Complete
D2
0 = Measuring data rate
1 = Measurement complete
Ratio
D4
Set
to 0
D2
Data Rate
Measure
Complete
0
Config. LOS
Reset MISC[2]
D3
Write a 1 followed by 0
to reset MISC[2]
D1
x
0
SQUELCH
Mode
Data Rate
Measure
Lock to Reference
D0
0 = Lock to input data
1 = Lock to reference clock
Output Boost
D0
0 = Default output swing
1 = Boost output swing
COARSE_RD[1]
D1
x
D0
LSB
LSB
LSB
COARSE_RD[0] LSB
Lock to
Reference
0
Output Boost
D2
Set
to 0
Coarse Rate
Readback LSB
D0
COARSE_RD[0]
ADN2813
D1
Set
to 0
D0
Set
to 0