ADN2892 Analog Devices, Inc., ADN2892 Datasheet

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ADN2892

Manufacturer Part Number
ADN2892
Description
3.3 V 4.25 Gb/s Limiting Amplifier
Manufacturer
Analog Devices, Inc.
Datasheet
FEATURES
Input sensitivity: 3.5 mV p-p
70 ps rise/fall times
CML outputs: 750 mV p-p differential
Bandwidth selectable for multirate 1×/2×/4× FC modules
Optional LOS output inversion
Programmable LOS detector: 3.5 mV to 35 mV
Rx signal strength indicator (RSSI)
Single-supply operation: 3.3 V
Low power dissipation: 160 mW
Available in space-saving, 3 mm × 3 mm, 16-lead LFCSP
Extended temperature range: −40°C to +95°C
SFP reference design available
APPLICATIONS
1×, 2×, and 4× FC transceivers
SFP/SFF/GBIC optical transceivers
GbE transceivers
Backplane receivers
Rev. 0.
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
SFF-8472-compliant average power measurement
ADN2882
PD_CATHODE
PD_VCC
PIN
NIN
Figure 1. RSSI Function Capable—Applications Setup Block Diagram
50Ω
ADN2892
AVCC
3.5kΩ
FUNCTIONAL BLOCK DIAGRAM
50Ω
AVEE
V
REF
LPF
BW_SEL
DETECTOR
RSSI/LOS
GENERAL DESCRIPTION
The ADN2892 is a 4.25 Gbps limiting amplifier with integrated
loss of signal (LOS) detection circuitry and a received signal
strength indicator (RSSI). This part is optimized for Fibre
Channel (FC) and Gigabit Ethernet (GbE) optoelectronic
conversion applications. The ADN2892 has a differential input
sensitivity of 3.5 mV p-p and accepts up to a 2.0 V p-p
differential input overload voltage. The ADN2892 has current
mode logic (CML) outputs with controlled rise and fall times.
The ADN2892 has a selectable low-pass filter with a −3 dB
cutoff frequency of 1.5 GHz. By setting BW_SEL to Logic 0, the
filter can limit the relaxation oscillation of a low cost CD laser
used in a legacy 1 Gbps FC transmitter. The limited BW also
reduces the rms noise and in turn improves the receiver optical
sensitivity for a lower data rate application, such as 1× FC and
GbE.
By monitoring the bias current through a photodiode, the on-
chip RSSI detector measures the average power received with
2% typical linearity over the entire valid input range of the
photodiode. The on-chip RSSI detector facilitates SFF-8472-
compliant optical transceivers by eliminating the need for
external RSSI detector circuitry.
Additional features include a programmable loss-of-signal
(LOS) detector and output squelch. The ADN2892 is available
in a 3 mm × 3 mm, 16-lead LFCSP.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
SQUELCH
THRADJ
DRVCC DRVEE
50Ω
©2005 Analog Devices, Inc. All rights reserved.
LOS_INV
50Ω
Limiting Amplifier
3.3 V, 4.25 Gbps,
OUTP
OUTN
RSSI_OUT
LOS
V+
10kΩ
ADN2892
ADuC7020
www.analog.com

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ADN2892 Summary of contents

Page 1

... The ADN2892 has current mode logic (CML) outputs with controlled rise and fall times. The ADN2892 has a selectable low-pass filter with a −3 dB cutoff frequency of 1.5 GHz. By setting BW_SEL to Logic 0, the filter can limit the relaxation oscillation of a low cost CD laser used in a legacy 1 Gbps FC transmitter ...

Page 2

... ADN2892 TABLE OF CONTENTS Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Typical Performance Characteristics ............................................. 7 Theory of Operation ...................................................................... 10 Limiting Amplifier ..................................................................... 10 Loss-of-Signal (LOS) Detector ................................................. 10 Received Signal Strength Indicator (RSSI).............................. 10 REVISION HISTORY 4/05—Revision 0: Initial Version Squelch Mode ............................................................................. 10 BW_SEL (Bandwidth Selection) Mode................................... 10 LOS_INV (Lose of Signal_Invert) Mode ...

Page 3

... V p-p 70 103 ps Rev Page ADN2892 Test Conditions/Comments At PIN or NIN, dc-coupled DC-coupled PIN − NIN, ac-coupled −10 PIN − NIN, BER ≤ 1 × 10 Single-ended Differential Differential, f < 4.25 GHz Differential, f < 4.25 GHz Input ≥ p-p, 4× FC, K28.7 pattern Input ≥ ...

Page 4

... ADN2892 Parameter LOGIC INPUTS (SQUELCH, LOS_INV, AND BW_SEL Input High Voltage Input Low Voltage IL Input Current (SQUELCH, LOS_INV) Input Current (BW_SEL) LOGIC OUTPUTS (LOS Output High Voltage Output Low Voltage OL Min Typ Max Unit 2 µA −38 µA 2.4 V 0.4 V Rev Page ...

Page 5

... J-STD-20 THERMAL RESISTANCE 125°C θ is specified for 4-layer PCB with exposed paddle soldered JA to GND. Table 3. Package Type 3 mm × 3 mm, 16-lead LFCSP Rev Page ADN2892 θ Unit JA 28 °C/W ...

Page 6

... PD_VCC P 16 PD_CATHODE AO Exposed Pad Pad power digital input digital output analog input; and AO = analog output AVCC DRVCC 1 12 ADN2892 PIN OUTP 2 11 TOP VIEW NIN OUTN 3 10 (Not to Scale) AVEE DRVEE Figure 2. Pin Configuration ...

Page 7

... TYPICAL PERFORMANCE CHARACTERISTICS 50ps/DIV Figure 3. Eye of ADN2892 @ 25°C, 4.25 Gbps, and 10 mV Input 50ps/DIV Figure 4. Eye of ADN2892 @ 95°C, 4.25 Gbps, and 10 mV Input 200ps/DIV Figure 5. Eye of ADN2892 at 25°C, 1.063 Gbps, and 10 mV Input (BW_SEL = 0) 0.06 +95°C 0.05 +25°C 0.04 0.03 –40°C 0.02 –40°C 0.01 +25°C +95° ...

Page 8

... ADN2892 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 1.0 1.5 2.0 2.5 3.0 RATE (Gbps) Figure 9. Random Jitter vs. Data Rate 1.0 1.5 2.0 2.5 3.0 RATE (Gbps) Figure 10. Deterministic Jitter vs. Data Rate 100k 1M SUPPLY-NOISE FREQUENCY Figure 11. PSRR vs. Supply-Noise Frequency 1200 1000 800 600 400 200 0 3.5 4.0 4.5 0 PD_CATHODE CURRENT (PHOTODIODE CURRENT) (µA) Figure 12 ...

Page 9

... PD_CATHODE (Input) Current of 5 µA 5.0 4.5 4.0 3.5 3.0 2.5 +100 ° C 2.0 1.5 1.0 0 200 400 600 PD_CATHODE CURRENT ( µ A) Figure 16. RSSI Linearity % vs. PD_CATHODE Current 49.0 48.5 48.0 47.5 47.0 46.5 46 100 –40 +30 ° C –40 ° C 800 1000 Rev Page ADN2892 – TEMPERATURE (°C) Figure 17. ADN2892 I Current vs. Temperature CC 100 80 ...

Page 10

... VCC − 0.7 V common-mode voltage and ±0.5 V headroom. If the input common-mode voltage is 2.4 V, the available headroom is reduced down to ±0.3 V. The ADN2892 limiting amplifier is a high gain device susceptible to dc offsets in the signal path. The pulse width distortion presented in the NRZ data or a distortion generated by the TIA may appear as dc offset or a corrupted signal to the ADN2892 inputs ...

Page 11

... C1–C4, C11: 0.01µF X5R/X7R DIELECTRIC, 0201 CASE C5, C7, C9, C10, C12: 0.1µF X5R/X7R DIELECTRIC, 0402 CASE C6, C8: 1nF X5R/X7R DIELECTRIC, 0201 CASE R3 4.7kΩ TO 10kΩ C12 R2 ON HOST BOARD VCC Figure 18. Typical ADN2892 Applications Circuit Rev Page RSSI MEASUREMENT TO ADC C10 VCC ...

Page 12

... Pad Coating Pb-Free Reflow Portfolio R1, C9, C10 ON BOTTOM AVCC 1 EXPOSED PAD C6 FILLED VIAS TO GND VIAS TO BOTTOM Figure 19. Recommended ADN2892 PCB Layout (Top View) Rev Page Matt-Tin J-STD-20B DVCC GND DOUBLE-VIAS TO REDUCE INDUCTANCE TO SUPPLY AND GND PLACE C7 ON BOTTOM OF BOARD UNDERNEATH C8 ...

Page 13

... Body, Very Thin Quad (CP-16-3) Dimensions shown in millimeters Package Description 16-Lead LFCSP, 500 pieces 16-Lead LFCSP, 1,500 pieces 16-Lead LFCSP, 5,000 pieces Evaluation Board Rev Page 0.50 0.40 0. 1.50 SQ 1.35 EXPOSED PAD 9 (BOTTOM VIEW 0.25 MIN Package Option CP-16-3 CP-16-3 CP-16-3 ADN2892 Branding F05 F05 F05 ...

Page 14

... ADN2892 NOTES Rev Page ...

Page 15

... NOTES Rev Page ADN2892 ...

Page 16

... ADN2892 NOTES ©2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04986–0–4/05(0) Rev Page ...

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