MBM30LV0032 Fujitsu Microelectronics, Inc., MBM30LV0032 Datasheet
MBM30LV0032
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MBM30LV0032 Summary of contents
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... The I/O pins are utilized for both address and data input/output as well as command inputs. The MBM30LV0032 is an ideal solution for applications requiring mass non-volatile storage such as solid state file storage, digital recording, image file memory for still cameras, and other uses which require high density and non-volatile storage ...
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... MBM30LV0032 FEATURES • 3.3 V-only operating voltage (2 3.6 V) Minimizes system level power requirements • Organization Memory Cell Array : (4M + 128K) 8 bit Data Register : (512 + 16) 8 bit • Automatic Program and Erase Page Program : (512 + 16) Byte Block Erase : (8K + 256) Byte • 528 Byte Page Read Operation Random Access : 7 s (Max ...
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... I/O3 Vss 22 23 FPT-44P-M07 MBM30LV0032 TOP VIEW Vcc 44 Vcc R N.C. 39 N.C. N.C. 38 N.C. N.C. 37 N.C. N.C. 36 N.C. N. N.C. N.C. 31 N.C. N.C. 30 N.C. N.C. N.C. 29 N.C. 28 N.C. N.C. 27 I/O7 I/O7 26 I/O6 I/O6 25 I/O5 I/O5 24 ...
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... MBM30LV0032 PIN DESCRIOTIONS Pin Number Pin Name Data Input/Output The I/O ports are used for transferring command, address, and input/output data I/ into and out of the device. The I/O pins will be high impedance when the outputs are disabled or the device is not selected. ...
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... BLOCK DIAGRAM High Voltage Pumps ALE CLE SE WP State Machine Command Register Address Register Status Register MBM30LV0032 Y-Decoder Data Register & S/A Memory Array Data Register & S/A Y-Decoder I/O Register & Buffer R/B I/O0 to I/O7 5 ...
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... MBM30LV0032 SCHEMATIC CELL LAYOUT AND ADDRESS ASSIGNMENT The Program operation is implemented in page units while the Erase operation is carried out in block units. Register Memory Cell Array I/O0 First Cycle A 0 Second Cycle A 9 Third Cycle column address page address ...
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... Read Mode Operation Status * ALE MBM30LV0032 ...
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... MBM30LV0032 COMMAND OPERATION Function Read (1) Read (2) Read (3) Sequential Data Input Page Program Block Erase Reset Status Read ID Read *1: The 00h Command defines starting Address on the 1st half Page. *2: The 01h Command defines starting Address on the 2nd half Page. *3: The 50h Command is valid only When SE is low level. ...
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... The Read (1), (2) mode is invoked by latching the 00h or 01h command into the command register. This mode (00h) will be automatically selected when the device powers up. CE CLE ALE WE RE R/B I/O0 to I/O7 Command 01h 00h Page (Row) X Address Figure 2 Starting Address 255 511 527 Y Y (Column Address) Read Mode (1), (2) Operation MBM30LV0032 = 0 while 01h sets Data Output 9 ...
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... MBM30LV0032 Read (3): 50h The Read (3) mode has identical timing to that of Read (1) and (2). However, while Read (1) and (2) are used to access the array, Read (3) is used to access the 16 byte spare area. When the 50h command is executed, the pointer will be set to an address space between columns 512 and 527. The values of Y will complete the address decoding. During this operation, only address bits A address ...
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... Upon completion, the Status Register bit I/O0 should be used to verify a successful erase. R/B I/O0 to I/O7 60h 10h Figure 5 Page Program to A are don’t care bits. Once the block address is successfully loaded Address Input D0h Figure 6 Block Erase MBM30LV0032 70h I/ Pass 1 = Fail 70h I/ Pass 1 = Fail 11 ...
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... MBM30LV0032 Read ID: 90h This mode allows the identification of the manufacturer and product. After the 90h command cycle, one address cycle follows in which 00h is entered. The next two RE pulses will output the manufacturer and device code respectively. RE I/O0 to I/O7 90h I/O7 Manufacturer 0 Device 1 Status Read: 70h The Status Register may be used to determine if the device is ready, in the write protect mode, or passed program/erase operations ...
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... Status Register will be set to C0h reset command is issued while the device is in the reset state, the command will be ignored. If the device is reset during the program or erase operations, the internal high voltages will be discharged before R/B goes high. R/B I/O0 to I/O7 FFh CE(2) CE(N) Device(2) Device(N) 0/1 70h Status of Device(1) Status of Device(N) Figure 8 Status Read MBM30LV0032 8 I/O0 to I/O7 R/B 0/1 13 ...
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... MBM30LV0032 ABSOLUTE MAXIMUM RATINGS Parameter Ambient Temperature with Power Applied Storage Temperature Voltage on a I/O pin with respect to Ground * Voltage on a pin except I/O with respect to Ground * Power Supply Voltage *: Minimum DC voltage on input or I/O pins is 0.5V. During voltage transitions, inputs may undershoot Vss to 2.0 V for periods ns. Maximum DC voltage on input pins is V ...
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... 3 3 OUT I/O pins V IH Except I/O pins V — –400 2 0 MBM30LV0032 Value Unit Min. Typ. Max. — — — — — — — — µ ...
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... MBM30LV0032 2. AC Characteristics (Note 1) Parameter CLE Setup Time CLE Hold Time CE Setup Time CE Hold Time Write Pulse Width ALE Setup Time ALE Hold Time Data Setup Time Data Hold Time Write Cycle Time WE High Hold Time WP High to WE Low Ready to RE Falling Edge ...
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... CRY t RST V = 2 3 2.4 V/0.4 V 1.5 V/1.5 V 1.5 V/1.5 V 1TTL 50 pF 100 100 ns CEH 526 527 510 511 Busy MBM30LV0032 Value Unit Min. Max. 50 — ns — 100 — ns (R/B) — 5/10/500 Busy signal is not output. 17 ...
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... Refer to Application Note (10) toward the end of this document. *2: Refer to Application Note (13) toward the end of this document. This specification is on conditions that ECC system would be combined. VALID BLOCKS The MBM30LV0032 occasionally contains unusable blocks. Refer to Application Note (12) toward the end of this document. Parameter Valid Block Number ...
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... CH t ALH t DH Command Input Cycle Timing Diagram Address Input Cycle Timing Diagram MBM30LV0032 : ALH ...
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... MBM30LV0032 CLE CE t ALS ALE WE I/ GND input : input : Figure N 527 IN 511 IN Data Input Cycle Timing Diagram t CLH ...
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... Figure REH REA t t RHZ RHZ Serial Read Cycle Timing Diagram t CLS t CLH CSTO t WHR RSTO 70h Status Read Cycle Timing Diagram MBM30LV0032 CHZ t REA t RHZ t CHZ t RHZ Status Output : ...
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... MBM30LV0032 CLE t CLS t CLH ALS ALE t ALH I/ 00h A to I/O7 7 Column address R/B **:SE = GND input : input : D CC Note: The CE signal must stay “Low” after the third address input and during Busy state. ...
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... AR2 ALH 527 OUT CC Read Cycle (3) Timing Diagram MBM30LV0032 REA ** OUT OUT OUT 256 + M 256 + REA ** OUT OUT OUT 512 + M 512 + 527 ...
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... MBM30LV0032 CLE CE WE ALE RE I/O0 00h to I/O7 Column Address R/B **: SE = GND input : input : D CC Note: The CE signal must stay “Low” after the third address input and during Busy state. Figure 18 CLE CE WE ALE RE I/O0 A 01h to I/O7 Column Address R/B **: SE = GND input : input : D CC Note: The CE signal must stay “ ...
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... Note: The CE signal must stay “Low” after the third address input and during Busy state. Figure 20 Sequential Read Cycle (3) Timing Diagram 512 512 512 Page Page M Access Access MBM30LV0032 ** 512 513 514 : ...
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... MBM30LV0032 t CLS CLE t t CLS CLS ALS t ALH ALE I/ 80h to I/ GND input : input : Figure 21 CLE t CLS t CLS t CLH ALS ALE I/ 60h A to I/O7 16 R/B Auto Block Erase ...
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... CLE t CLS CLS ALS t ALH ALE I/O0 90h to I/O7 Address Input Figure 23 t ALH AR1 00h 04h E3h t t REAID REAID Maker Code Device Code ID Read Operation Timing Diagram MBM30LV0032 : ...
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... MBM30LV0032 APPLICATION NOTES AND COMMENTS (1) Prohibition of unspecified commands The operation commands are listed in Table 4. Data input as a command other than the specified commands in Table 4 is prohibited. Stored data may be corrupted if an unspecified command is entered during the command cycle. (2) Pointer Action for Program Operation The pointer action can be done for program operation as follows ...
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... If programming at page address (M) fails, data should be programmed at the page address (N) of another block. Data input at first programming at page address (M) is lost. So address input using the 80h command must follow the same procedure as data input. Figure 27 Auto Program Failure MBM30LV0032 00 [A] Status read Status output 10 ...
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... MBM30LV0032 (6) R/B: Termination of the Ready/Busy pin (R/B) The R/B is open-drain output. When using the R/B, R/B must be pulled up V (7) Power On/Off Sequence: After power-off, each input signal level may be undefined. Use the WP signal as shown in the figure below. 2 DON’T CARE CE, WE, RE CLE, ALE ...
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... A Low-level WP signal will force erasing and programming to be reset. To control, use the WP signal as shown below. Program WE DIN WP R/B Program Prohibition WE DIN WP R/B Erase WE DIN WP R/B Erase Prohibition WE DIN WP R 100 ns (Min 100 ns (Min 100 ns (Min 100 ns (Min.) MBM30LV0032 31 ...
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... MBM30LV0032 (9) Address input in 4 cycles The device will get addresses in three cycles. If addresses are input in four cycles, address input in the fourth cycle will be ignored in the chip. Read operation CLE CE WE ALE I/O0 to I/O7 00h, 01h or 50h R/B Internal read operation starts when WE in the third cycle goes high. ...
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... Input” or “1” Column B Column C Column D Data Pattern 2 ‘1’ ‘1’ Divided Program in the Same Page Figure 33 RE Input Before Address MBM30LV0032 “No Input” or “1” Column E Column F Data Pattern 3 “No Input” or “1” Column E Column F Data Pattern 3 ‘ ...
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... If an error occurs at erasing, like programming, remedies should be executed on a system basis to prevent access to blocks causing the error. 34 Some MBM30LV0032 products have invalid blocks (bad blocks) at shipping. After mounting the device in the system, test whether there are no bad blocks. If there are any bad blocks, they should not be accessed ...
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... The ALE input must remain high once asserted until the last address byte has been written to the device. Read Operation CLE CE WE ALE I/O0 to I/O7 Program Operation CLE CE WE ALE I/O0 to I/O7 Erase Operation CLE CE WE ALE I/O0 to I/O7 00h, 01h or 50h Address Input 80h Address Input 60h Address Input MBM30LV0032 Keep H Inhibit L Input Keep H Inhibit L Input Keep H Inhibit L Input D0h 35 ...
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... MBM30LV0032 (15) Inhibit RE Toggling during Busy State The RE input cannot be allowed to toggle during the period that a read data transfer operation is in process (busy state). If the RE input toggles during that period, the internal column address will increment. CE CLE ALE WE RE R/B I/O0 to I/O7 (16) Restriction on Toggling the WE The WE input cannot be allowed to toggle past the end of page (byte 511 with SE high or byte 527 with SE low) during an input data operation ...
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... Busy state. If the CE signal goes High during this period, the read operation will be terminated and then the standby mode will be entered OUT OUT MBM30LV0032 OUT OUT D OUT N+1 N 10h * : ...
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... MBM30LV0032 BAD BLOCK TEST FLOW Block No. = Block No Test Start Block No Page 1 & Blank Check ] ^ All FFh? Yes Yes > B No. 511 = No Test End Figure 36 Bad Block Test Flow Set as a bad block ...
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... PFTR = 44-Pin Thin Small Outline Package (TSOP) Reverse Pinout 8-Bit) CMOS Flash Memory Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult -PFTN the local Fujitsu sales office to confirm availability -PFTR of specific valid combinations and to check on newly released combinations. MBM30LV0032 39 ...
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... MBM30LV0032 PACKAGE DIMENSIONS 44-pin plastic TSOP (II) (FPT-44P-M07 INDEX LEAD No 18.41±0.10 (.725±.004) 0.30±0.10 0.13(.005) (.012±.004) 0.10(.004) 0.80(.0315)TYP 16.80(.661)REF 2000 FUJITSU LIMITED F44016S-1C Resin protrusion. (Each side: 0.15(.006) Max Details of "A" part "A" ...
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... Details of "A" part "A" 22 0(0)MIN 0.50±0.10 (STAND OFF) (.020±.004) +0.10 +.004 1.10 .043 –0.05 –.002 (Mounting height) M MBM30LV0032 0.15(.006) 0.25(.010) 0.15(.006)MAX 0.40(.016)MAX 10.76±0.20 (.424±.008) 0.15±0.05 (.006±.002) 10.16±0.10 (.400±.004) 11.76±0.20 (.463±.008) Dimensions in mm (inches) 41 ...
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... MBM30LV0032 FUJITSU LIMITED For further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS, INC. ...