MX26F128J3 ETC-unknow, MX26F128J3 Datasheet - Page 20

• Manufacturer Part Number: MX26F128J3
• Description: Macronix Nbit Tm Memory Family 128m [x8/x16] Single 3v Page Mode Eliteflash Tm Memory
• Manufacturer: ETC-unknow

READ STATUS REGISTER COMMAND
The Status Register is read after writing the Read Status
Register command of 70H to the Command User Inter-
face. Also, after starting the internal operation the de-
vice is set to the Read Status Register mode automati-
cally.
The contents of Status Register are latched on the later
falling edge of OE or the first edge of CE0, CE1, CE2
that enables the device OE must be toggle to VIH or the
device must be disable before further reads to update
the status register latch. The Read Status Register com-
mand functions independently of the VPEN voltage.
CLEAR STATUS REGISTER COMMAND
The Erase Status, Program Status, Block Status bits
and protect status are set to "1" by the Write State Ma-
chine and can only be reset by the Clear Status Register
command of 50H. These bits indicates various failure
conditions.
P/N:PM0960
BLOCK ERASE COMMAND
Automated block erase is initiated by writing the Block
Erase command of 20H followed by the Confirm com-
mand of D0H. An address within the block to be erased
is required (erase changes all block data to FFH).
Block preconditioning, erase, and verify are handled in-
ternally by the WSM (invisible to the system). The CPU
can detect block erase completion by analyzing the out-
put of the STS pin or status register bit SR.7. Toggle OE,
CE0 , CE1 , or CE2 to update the status register. The
CUI remains in read status register mode until a new
command is issued. Also, reliable block erasure can only
occur when VCC is valid and VPEN = VPENH.
20
WRITE TO BUFFER COMMAND
To program the device, a Write to Buffer command is
issue first. A variable number of bytes, up to the buffer
size, can be loaded into the buffer and written to the
eLiteFlash
Setup command is issued along with the Block Address
(see Figure 4 ,"Write to Buffer Flowchart" on page26).
After the command is issued, the extended Status Reg-
ister (XSR) can be read when CE is VIL. XSR.7 indi-
cates if the Write Buffer is available.
If the buffer is available, the number of words/bytes to
be program is written to the device. Next, the start ad-
dress is given along with the write buffer data. Subse-
quent writes provide additional device addresses and
data, depending on the count. After the last buffer data
is given, a Write Confirm command must be issued. The
WSM beginning copy the buffer data to the eLiteFlash
memory array.
If an error occurs while writing, the device will stop writ-
ing, and status register bit SR.4 will be set to a "1" to
indicate a program failure. The internal WSM verify only
detects errors for "1" that do not successfully program
to "0" . If a program error is detected, the status register
should be cleared. Any time SR.4 and/or SR.5 is set, the
device will not accept any more Write to Buffer com-
mands. Reliable buffered writes can only occur when VCC
is valid and VPEN = VPENH. Also, successful program-
ming requires that the corresponding block lock-bit be
reset.
BYTE/WORD PROGRAM COMMANDS
Byte/Word program is executed by a two-command se-
quence. The Byte/Word Program Setup command of 40H
is written to the Command Interface, followed by a sec-
ond write specifying the address and data to be written.
The WSM controls the program pulse application and
verify operation. The CPU can detect the completion of
the program event by analyzing the STS pin or status
register bit SR.7.
If a byte/word program is attempted while VPEN_V
PENLK, status register bits SR.4 and SR.3 will be set to
"1". Successful byte/word programs require that the cor-
responding block lock-bit be cleared. If a byte/ word pro-
gram is attempted when the corresponding block lock-
bit is set, SR.1 and SR.4 will be set to "1".
TM
memory device. First, the Write to Buffer
MX26F128J3
REV. 1.1,OCT. 18, 2004
TM