IS61C64AL Integrated Silicon Solution, Inc., IS61C64AL Datasheet - Page 8
IS61C64AL
Manufacturer Part Number
IS61C64AL
Description
8k X 8 High-speed Cmos Static Ram
Manufacturer
Integrated Silicon Solution, Inc.
Datasheet
1.IS61C64AL.pdf
(13 pages)
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IS61C64AL
WRITE CYCLE NO. 2
WRITE CYCLE NO. 3
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
2. I/O will assume the High-Z state if OE
8
ADDRESS
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
ADDRESS
D
D
OUT
WE
D
OE
CE
OUT
WE
D
OE
CE
IN
IN
LOW
LOW
LOW
t
SA
t
DATA UNDEFINED
SA
DATA UNDEFINED
(OE is HIGH During Write Cycle)
(OE is LOW During Write Cycle)
≥
V
IH
.
VALID ADDRESS
t
t
t
t
AW
HZWE
AW
HZWE
VALID ADDRESS
t
t
PWE1
WC
t
t
PWE2
(1)
(1,2)
WC
HIGH-Z
Integrated Silicon Solution, Inc. — 1-800-379-4774
HIGH-Z
t
t
SD
SD
DATA
DATA
IN
IN
VALID
VALID
t
t
HD
HD
t
t
LZWE
LZWE
t
t
HA
HA
ISSI
CE_WR2.eps
CE_WR3.eps
10/23/06
Rev. B
®