IS61LV6416 Integrated Silicon Solution, Inc., IS61LV6416 Datasheet
IS61LV6416
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IS61LV6416 Summary of contents
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... Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS61LV6416/IS61LV6416L is packaged in the JEDEC standard 44-pin 400-mil SOJ, 44-pin TSOP-II, and 48-pin mini BGA (6mm x 8mm). A0-A15 ...
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... IS61LV6416 IS61LV6416L PIN CONFIGURATIONS 44-Pin SOJ (K) A15 A14 A13 A12 A11 I/ I/O15 I/ I/O14 I/ I/O13 I/ I/O12 VDD 11 34 GND GND 12 33 VDD I/ I/O11 I/ I/O10 I/ I/ ...
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... IS61LV6416 IS61LV6416L TRUTH TABLE Mode Not Selected X Output Disabled H X Read Write ABSOLUTE MAXIMUM RATINGS Symbol Parameter V Terminal Voltage with Respect to GND TERM T Storage Temperature STG P Power Dissipation Output Current (LOW) OUT Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device ...
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... IN ≤ 0.2V Note address and data inputs are cycling at the maximum frequency means no input lines change. MAX 2. Typical values are measured IS61LV6416L POWER SUPPLY CHARACTERISTICS Symbol Parameter Test Conditions I V Dynamic Operating Supply Current ...
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... IS61LV6416 IS61LV6416L AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load AC TEST LOADS 319 Ω 3.3V OUTPUT 30 pF Including jig and scope Figure 1a. READ CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Read Cycle Time ...
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... IS61LV6416 IS61LV6416L AC WAVEFORMS (Address Controlled) ( (1,2) READ CYCLE NO. 1 ADDRESS D OUT PREVIOUS DATA VALID READ CYCLE NO. 2 (1,3) ADDRESS LZCE LB LZB HIGH-Z D OUT Notes HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE, UB Address is valid prior to or coincident with CE LOW transition. ...
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... IS61LV6416 IS61LV6416L WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Write Cycle Time Write End t SCE t Address Setup Time AW to Write End t Address Hold from Write End HA t Address Setup Time SA LB, UB Valid to End of Write t PBW WE Pulse Width (OE = HIGH/LOW PWE ...
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... IS61LV6416 IS61LV6416L (CE Controlled HIGH or LOW) (1,2) WRITE CYCLE NO. 1 ADDRESS UB DATA UNDEFINED OUT VALID ADDRESS t SCE PWE1 t PWE2 t PBW t HZWE HIGH DATA VALID IN ISSI ® LZWE HD UB_CEWR1.eps Integrated Silicon Solution, Inc. Rev. I 11/22/05 ...
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... IS61LV6416 IS61LV6416L (WE Controlled HIGH during Write Cycle) WRITE CYCLE NO. 2 (1) ADDRESS OE CE LOW UB DATA UNDEFINED OUT D IN WRITE CYCLE NO. 3 (WE Controlled LOW During Write Cycle) ADDRESS OE LOW CE LOW UB DATA UNDEFINED OUT D IN Integrated Silicon Solution, Inc. ...
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... IS61LV6416 IS61LV6416L (LB, UB Controlled, Back-to-Back Write) WRITE CYCLE NO. 4 ADDRESS OE CE LOW WE UB HZWE D OUT DATA UNDEFINED D IN Notes: 1. The internal Write time is defined by the overlap LOW, UB and/ LOW, and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The referenced to the rising or falling edge of the signal that terminates the Write ...
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... DR CE GND Integrated Silicon Solution, Inc. Rev. I 11/22/05 Test Condition Options See Data Retention Waveform = 2.0V, CE ≥ – 0.2V IS61LV6416 DD DD IS61LV6416L See Data Retention Waveform See Data Retention Waveform = 3.0V and not 100% tested (CE Controlled) t Data Retention Mode SDR CE ≥ 0.2V DD ISSI ® ...
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... IS61LV6416-8KL 10 IS61LV6416-10T 10 IS61LV6416-10TL 10 IS61LV6416-10K 10 IS61LV6416-10BI 10 IS61LV6416-10BLI 10 IS61LV6416-10TI 10 IS61LV6416-10TLI 10 IS61LV6416-10KI 10 IS61LV6416-10KLI 12 IS61LV6416-12T 12 IS61LV6416-12K 12 IS61LV6416-12KL 12 IS61LV6416-12BI IS61LV6416L ORDERING INFORMATION Speed (ns) Order Part No. 8 IS61LV6416L-8T 8 IS61LV6416L-8BI 8 IS61LV6416L-8TI 8 IS61LV6416L-8KI 10 IS61LV6416L-10T 10 IS61LV6416L-10BI 10 IS61LV6416L-10TI 10 IS61LV6416L-10KI 12 Package Temperature Range Plastic TSOP Commercial (0°C to +70°C ) Plastic TSOP Commercial (0°C to +70°C ), Lead-free mini BGA (6mm x 8mm) Industrial (-40° ...
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... BSC Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — ...
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... BSC Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products ...
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... Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — ...
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... Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — ...