A3981 Allegro Micro Systems, Inc., A3981 Datasheet - Page 14

• Manufacturer Part Number: A3981
• Manufacturer: Allegro Micro Systems, Inc.

Configuration
Register 0
(CONFIG0)
Configuration
Register 1
(CONFIG1)
Run Register
(RUN)
Table Load
Register
(TBLLD)
Fault
Register 0
(FAULT0)
A3981
A three wire synchronous serial interface, compatible with
SPI, can be used to configure and control all the features of the
A3981. A fourth wire can be used to provide diagnostic feedback.
The registers that are accessible through the serial interface are
defined in table 2.
The A3981 can be operated without using the serial interface,
by using the default configuration and control register settings
and the STEP and DIR logic inputs for motor control. However,
application-specific configurations are only possible by setting
the appropriate register bits through the serial interface. In addi-
tion to setting the configuration bits, the serial interface can also
be used to control the motor directly.
The serial interface timing requirements are specified in the Elec-
trical Characteristics table, and illustrated in figure 1.
Table 2. Serial Register Definition*
Configuration and Control Registers (Write)
Diagnostic Registers (Read)
Fault
Register 1
(FAULT1)
*Power-on reset value shown below each input register bit.
FF
FF
15
0
0
1
1
TW1
TW1
14
0
1
0
1
OSC
SYR
TW0
TW0
EN
13
0
0
1
0
TSC1
MS1
OL1
OV
OV
12
0
1
0
0
TSC0
MS0
OL0
UV
UV
11
0
0
1
0
Serial Interface Description
Automotive, Programmable Stepper Driver
MXI1
HLR
ST
ST
10
1
0
0
0
SLEW
MXI0
OLB
OLB
9
1
0
1
0
PFD2
BRK
OLA
OLA
8
1
0
0
0
Writing to Configuration and Control Registers
When writing to the serial register, data is received on the SDI
pin and clocked through a shift register on the rising edge of the
clock signal input on the SCK pin. STRn is normally held high,
and is only brought low to initiate a serial transfer. No data is
clocked through the shift register when STRn is high, thus allow-
ing multiple SDI slave units to use common SDI, SCK, and SDO
connections. Each independent slave requires a dedicated STRn
connection.
The serial data word has 16 bits, MSB input first. After 16 data
bits have been clocked into the shift register, STRn must be taken
high to latch the data into the selected register. When this occurs,
the internal control circuits act on the new configuration and
control data, and the diagnostic registers are reset.
DCY1
PFD1
BML
7
0
0
0
0
0
DCY0
PFD0
BMH
PTP
6
0
0
1
1
0
TBK1
CD3
SC5
SA5
PT5
BPL
5
0
1
0
0
115 Northeast Cutoff
1.508.853.5000; www.allegromicro.com
Allegro MicroSystems, Inc.
Worcester, Massachusetts 01615-0036 U.S.A.
TBK0
BPH
CD2
SC4
SA4
PT4
4
1
0
0
0
FRQ2
TOF2
CD1
SC3
AML
PT3
SA3
3
1
0
0
0
TOF1
FRQ1
AMH
CD0
SC2
PT2
SA2
2
1
0
0
0
DIAG1 DIAG0
FRQ0
TOF0
SC1
PT1
APL
SA1
1
0
0
0
0
PWM
APH
SC0
PT0
SA0
0
0
0
0
0
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