APL5913 Anpec Electronics, APL5913 Datasheet - Page 14

• Manufacturer Part Number: APL5913
• Description: 0.8V Reference Ultra Low Dropout Linear Regulator
• Manufacturer: Anpec Electronics

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APL5913
Feedback Network (Cont.)
Copyright
Rev. A.4 - May., 2005
Application Information (Cont.)
R1
C1
• Condition 3 : Low ESR (eg. Ceramic Capacitors)
C1
- Calculate the C1 as the following :
- The C1 calculated from equation (4) must meet
- Use equation (2) to calculate the R2.
- Calculate the R1 as the following:
- Calculate the C1 as the following :
- The C1 calculated from equation (7) must meet
(pF)
(k
the following equation :
C1
Select a proper R1(selected) to be a little larger
than the calculated R1.
Select a proper C1(selected) to be a little smaller
than the calculated C1.
If the C1(calculated) can not meet the equation
(5), please use the Condition 3.
Select a proper R1(selected) to be a little larger
than the calculated R1. The minimum selected
R1 is equal to 1k
smaller than 1k or negative.
Select a proper C1(selected) to be a little smaller
than the calculated C1.
(pF)
the following equation:
Where R1=R1(selected)
Where R1=R1(calculated) from equation (3)
Where R1=R1(selected)
Where R1=R1(calculated) from equation (6)
)
C1
(pF)
(0.24
(pF)
(2.1
0.033
7.2
ANPEC Electronics Corp.
0.71
ESR
ESR
1
1.25
(m
(m
ESR
ESR
)
)
143
R1
(m
300)
34.2)
(m
V
(k
when the calculated R1 is
OUT(V)
)
)
)
101
C
C
1
OUT(uF)
OUT(uF)
ESR
C
37.5
R1
OUT(uF)
(k
R1
(m
1
37.5
)
V
(k
)
37.5
OUT(V)
........
)
C
V
OUT(uF)
R1
OUT(V)
V
(k
..
(4)
OUT(V)
)
(5)
..
..
(8)
(6)
..
14
(7)
The reason to have three conditions described above
is to optimize the load transient responses for all kinds
of the output capacitor. For stability only, the Condition
2, regardless of equation (5), is enough for all kinds of
output capacitor.
PCB Layout Considerations (See Figure 2)
1. Please solder the Exposed Pad and VIN together
2. Please place the input capacitors for VIN and
3. Ceramic decoupling capacitors for load must be
4. To place APL5913 and output capacitors near the
5. The negative pins of the input and output capaci-
6. Please connect PIN 3 and 4 together by a wide
7. Large current paths must have wide tracks.
8. See the Typical Application
(see next page Figure 2)
on the PCB. The main current flow is through the
exposed pad. Refer Figure 3 to make a proximate
topology.
VCNTL pins near pins as close as possible.
placed near the load as close as possible.
load is good for performance.
tors and the GND pin of the APL5913 are connected
to the ground plane of the load.
track.
- Connect the one pin of the R2 to the GND of
APL5913
- Connect the one pin of R1 to the Pin 3 of APL5913
- Connect the one pin of C1 to the Pin 3 of APL5913
- Use equation (2) to calculate the R2.
If the C1
please use the Condition 2.
(calculated)
can not meet the equation (8),
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