MC74HC541ADWG ON Semiconductor, MC74HC541ADWG Datasheet - Page 4

• Manufacturer Part Number: MC74HC541ADWG
• Description: IC BUFF/DVR TRI-ST 8BIT 20SOIC
• Manufacturer: ON Semiconductor
• Series: 74HCr

Specifications of MC74HC541ADWG

• Logic Type: Buffer/Line Driver, Non-Inverting
• Number Of Elements: 1
• Number Of Bits Per Element: 8
• Current - Output High, Low: 7.8mA, 7.8mA
• Voltage - Supply: 2 V ~ 6 V
• Operating Temperature: -55°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Logic Family: 74HC
• Number Of Channels Per Chip: Octal
• Polarity: Non-Inverting
• Supply Voltage (max): 6 V
• Supply Voltage (min): 2 V
• Maximum Operating Temperature: 125 C
• Mounting Style: SMD/SMT
• High Level Output Current: - 7.8 mA
• Input Bias Current (max): 4 uA
• Low Level Output Current: 7.8 mA
• Maximum Power Dissipation: 500 mW
• Minimum Operating Temperature: - 55 C
• Number Of Lines (input / Output): 3
• Output Type: 3-State
• Propagation Delay Time: 80 ns @ 2 V or 30 ns @ 3 V or 18 ns @ 4.5 V or 15 ns @ 6 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: MC74HC541ADWG; MC74HC541ADWGOS

8. Information on typical parametric values can be found in the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
9. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High−Speed
10. Used to determine the no−load dynamic power consumption: P
DC CHARACTERISTICS (Voltages Referenced to GND)
AC CHARACTERISTICS
Symbol
Symbol
C
t
t
t
t
V
t
t
t
C
V
t
PLH
CMOS Data Book (DL129/D).
Semiconductor High−Speed CMOS Data Book (DL129/D).
V
I
PLZ
PZL
TLH
C
V
I
PHL
PHZ
PZH
THL
I
OUT
OZ
CC
OH
IN
OL
PD
IH
IN
IL
,
,
,
,
Minimum High−Level Input Voltage
Maximum Low−Level Input Voltage
Minimum High−Level Output Voltage
Maximum Low−Level Output Voltage
Maximum Input Leakage Current
Maximum 3−State Leakage Current
Maximum Quiescent Supply
Current (per Package)
Maximum Propagation Delay, Input A to Output Y
(Figures 3 and 5)
Maximum Propagation Delay, Output Enable to Output Y
(Figures 4 and 6)
Maximum Propagation Delay, Output Enable to Output Y
(Figures 4 and 6)
Maximum Output Transition Time, Any Output
(Figures 3 and 5)
Maximum Input Capacitance
Maximum 3−State Output Capacitance (High Impedance State Output)
Power Dissipation Capacitance (Per Buffer) (Note 10)
Parameter
(C
L
= 50 pF, Input t
Parameter
r
= t
V
|I
V
|I
V
|I
V
V
|I
V
V
Output in High Impedance State
V
V
V
I
f
OUT
= 6 ns)
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
OUT
IN
= V
= V
= V
= V
= V
= V
= V
| ≤ 20 mA
| ≤ 20 mA
| ≤ 20 mA
| ≤ 20 mA
= 0 mA
http://onsemi.com
= 0.1 V
= V
= V
IL
IL
IH
IH
CC
IL
CC
CC
or V
CC
or GND
or GND
Condition
− 0.1 V
or GND
IH
4
D
|I
|I
|I
|I
|I
|I
= C
OUT
OUT
OUT
OUT
OUT
OUT
PD
| ≤ 3.6 mA
| ≤ 6.0 mA
| ≤ 7.8 mA
| ≤ 3.6 mA
| ≤ 6.0 mA
| ≤ 7.8 mA
V
CC
2
f + I
V
Typical @ 25°C, V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
V
CC
CC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
4.5
6.0
3.0
4.5
6.0
2.0
4.5
6.0
3.0
4.5
6.0
6.0
6.0
6.0
V
CC
V
CC
*55 to
25_C
110
110
. For load considerations, see the ON
80
30
18
15
45
25
21
45
25
21
60
22
12
10
10
15
*55 to
25_C
$0.1
$0.5
1.50
2.10
3.15
4.20
0.50
0.90
1.35
1.80
2.48
3.98
5.48
0.26
0.26
0.26
1.9
4.4
5.9
0.1
0.1
0.1
4
Guaranteed Limit
Guaranteed Limit
CC
35
v85_C
= 5.0 V, V
100
140
140
v85_C
40
23
20
60
31
26
60
31
26
75
28
15
13
10
15
$1.0
$5.0
1.50
2.10
3.15
4.20
0.50
0.90
1.35
1.80
2.34
3.84
5.34
0.33
0.33
0.33
1.9
4.4
5.9
0.1
0.1
0.1
40
EE
v125_C
v125_C
$10.0
$1.0
120
165
165
= 0 V
1.50
2.10
3.15
4.20
0.50
0.90
1.35
1.80
2.20
3.70
5.20
0.40
0.40
0.40
160
55
28
25
75
38
31
75
38
31
90
34
18
15
10
15
1.9
4.4
5.9
0.1
0.1
0.1
Unit
Unit
mA
mA
mA
pF
pF
pF
ns
ns
ns
ns
V
V
V
V