CMX138 CML Microcircuits, CMX138 Datasheet - Page 14

• Manufacturer Part Number: CMX138
• Description: Audio Scrambler and Sub-Audio Signalling Processor
• Manufacturer: CML Microcircuits

Audio Scrambler and Sub-Audio Signalling Processor
The number of data bytes following an Address byte is dependent on the value of the Address byte. The
most significant bit of the address or data are sent first. For detailed timings see section 11.2. Note that,
due to internal timing constraints, there may be a delay of up to 250μs between the end of a C-BUS write
operation and the CMX138 responding to the C-BUS command.
C-BUS Write:
CSN
Serial_Clock
CMD_DATA
REPLY_DATA
C-BUS Read:
CSN
Serial_Clock
CMD_DATA
REPLY_DATA
Notes:
© 2008 CML Microsystems Plc
1. For Command byte transfers only the first 8 bits are transferred ($01 = Reset).
2. For single byte data transfers only the first 8 bits of the data are transferred.
3. The CMD_DATA and REPLY_DATA lines are never active at the same time. The Address byte
4. The Serial_Clock input can be high or low at the start and end of each C-BUS transaction.
5. The gaps shown between each byte on the CMD_DATA and REPLY_DATA lines in the above
determines the data direction for each C-BUS transfer.
diagram are optional, the host may insert gaps or concatenate the data as required.
Repeated cycles
Either logic level valid (and may change)
Either logic level valid (but must not change from low to high)
Data value unimportant
MSB
MSB
7
7
Address / Command byte
6
6
5
5
Address byte
High Z state
High Z state
4
4
Figure 4 C-BUS Transactions
3
3
2
2
1
1
Page 14
LSB
LSB
0
0
See Note 1
MSB
MSB
7
7
Upper 8 bits
Upper 8 bits
6
6
…
…
LSB
LSB
0
0
See Note 2
See Note 2
MSB
MSB
Lower 8 bits
Lower 8 bits
7
7
…
…
LSB
LSB
0
0
D/138_FI1.0/5
CMX138