CMX605P3 CML Microcircuits, CMX605P3 Datasheet - Page 11

• Manufacturer Part Number: CMX605P3
• Description: Digital Line to POTS Interface
• Manufacturer: CML Microcircuits

Digital Line to POTS Interface
Failure to load the TX DATA Register with a new value when required will result in bit 7 (Tx Data
Underflow) of the STATUS Register being set to ‘1’. If the ‘Tx Async’ mode of operation is selected then
a continuous Mark (‘1’) signal will be transmitted until a new value is loaded into TX DATA. If the ‘Tx
Sync’ mode is selected then the byte already in the TX DATA Register will be re-transmitted.
2001 Consumer Microcircuits Limited
One Start bit (Space)
Eight Data bits (D0-D7) from the TX DATA Register, with the lsb (D0) transmitted first
One Stop bit (Mark)
Figure 3a Transmit UART Function (Async)
Figure 3b Transmit UART Function (Sync)
11
CMX605
D/605/6