CMX624 CML Microcircuits, CMX624 Datasheet - Page 12

• Manufacturer Part Number: CMX624
• Description: V.23-Bell 202 Modem
• Manufacturer: CML Microcircuits

V23 / Bell 202 Modem
Received data from the FSK Demodulator goes into the receive part of the UART block, where it is handled in
one of two ways depending on the setting of bit 7 of the FSK MODE Register:
Bit 2 (Rx Data Ready) of the FLAGS Register will be set to ‘1’ every time a new received value is loaded into
the RX DATA Register. If the previous contents of the RX DATA Register had not been read out over the ‘C-
BUS’ before the new value is loaded from the UART then bit 3 (Rx Data Overflow) of the FLAGS Register will
also be set to ‘1’.
2001 Consumer Microcircuits Limited
If the bit is ‘0’ (‘Rx Sync’ mode) then the receive part of the UART block will simply take 8 consecutive
bits from the Demodulator and transfer them to the RX DATA Register (the first bit going into the D0
position). Note that this mode is intended for detection of simple data patterns such as ‘1010…’ or
continuous Mark or Space signals, the CMX624’s receive data clock extraction circuits are not
adequate to support a true synchronous receive data mode of operation.
If bit 7 of the FSK MODE Register is ‘1’ (‘ Rx Async’) then the received data output of the FSK
Demodulator is treated as 75, 150 or 1200 bps asynchronous characters each comprising:
A Start bit (Space).
7 or 8 Data bits as determined by bit 0 of the SETUP Register. These bits will be placed into
the RX DATA Register with the first bit received going into the D0 position.
An optional Parity bit as determined by bits 1 and 2 of the SETUP Register. If Parity is
enabled (bit 2 of the SETUP Register = ‘1’) then bit 7 of the FLAGS Register will be set to ‘1’ if
the received parity is incorrect.
At least one Stop bit (Mark).
Figure 6b Receive UART Function (Async)
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CMX624
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