CMX649E3 CML Microcircuits, CMX649E3 Datasheet - Page 22
![no-image](/images/no-image-200.jpg)
CMX649E3
Manufacturer Part Number
CMX649E3
Description
ADM Codec
Manufacturer
CML Microcircuits
Datasheet
1.CMX649E3.pdf
(52 pages)
- Current page: 22 of 52
- Download datasheet (412Kb)
ADM Codec
CODEC MODE CONTROL Register ($70)
Reserved
(Bits 7 – 3)
CODEC MODE
(Bits 2 – 0)
SCRAMBLER CONTROL Register ($71)
Scrambler
Enable
(Bit 15)
Output
Scrambler
Pseudo Random
(Bit 14)
Scrambler
Output Invert
(Bit 13)
De-Scrambler
Enable
(Bit 12)
Output De-
Scrambler
Psuedo Random
(Bit 11)
De-Scrambler
Output Invert.
(Bit 10)
LFSR Tap
Select
(Bits 9 – 0)
2002 CML Microsystems Plc
These bits are reserved and should be set to a logic 0.
Setting this bit to a logic 1 enables the scrambler.
Setting this bit to a logic 1 forces the scrambler to put out a pseudo-random
sequence.
Setting this bit to a logic 1 inverts the scrambler output polarity.
Setting this bit to a logic 1 enables the de-scrambler.
Setting this bit to a logic 1 forces the de-scrambler to put out a pseudo-random
sequence.
Setting this bit to a logic 1 inverts the de-scrambler output polarity.
These bits directly program the polynomial for the scrambler and de-scrambler:
PR = B9X
Bit 2
0
0
0
0
1
1
1
1
9
+ B8X
Bit 1
0
0
1
1
0
0
1
1
8
+ B7X
Bit 0
0
1
0
1
0
1
0
1
7
+B6X
ADM mode without buffered I/O
ADM mode with buffered I/O
Linear PCM with buffered I/O
µ-law PCM with buffered I/O
A-law PCM with buffered I/O
A-law PCM with buffered I/O
A-law PCM with buffered I/O
A-law PCM with buffered I/O
22
6
+ B5X
CODEC Mode
5
+ B4X
4
+ B3X
3
+ B2X
2
+ B1X
1
+ B0X
CMX649
0
D/649/1
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