IDT6116LA120D Integrated Device Technology, Inc., IDT6116LA120D Datasheet - Page 9

• Manufacturer Part Number: IDT6116LA120D
• Description: CMOS Static RAM 16k ( 2k X 8 Bit )
• Manufacturer: Integrated Device Technology, Inc.

IDT6116SA/LA
CMOS STATIC RAM 16K (2K x 8-BIT)
TIMING WAVEFORM OF WRITE CYCLE NO. 1, (
NOTES:
1.
2. A write occurs during the overlap of a LOW
3. tWR is measured from the earlier of
4. During this period, the I/O pins are in the output state and the input signals must not be applied.
5. If the
6. Transition is measured 500mV from steady state.
7.
TIMING WAVEFORM OF WRITE CYCLE NO. 2, (
ADDRESS
ADDRESS
DATA
WE
OE
I/O drivers to turn off and data to be placed on the bus for the required t
apply and the write pulse is the specified t
DATA
DATA
is continuously HIGH. If
or
CS
CS
WE
OUT
CS
WE
CS
IN
IN
LOW transition occurs simultaneously with or after the
must be HIGH during all address transitions.
PREVIOUS DATA VALID
OE
is LOW during a
CS
or
t
t
AS
AS
WP
WE
CS
. For a
going HIGH to the end of the write cycle.
and a LOW
WE
CS
controlled write cycle, the write pulse width must be the larger of t
controlled write cycle,
t
WHZ
(4)
WE
(6)
.
t
AW
WE
t
WC
t
AW
LOW transition, the outputs remain in the high-impedance state.
t
t
DW
WC
WP
5.1
WE
WE
CS
t
CS
. If
CW
(7)
OE
OE
CONTROLLED TIMING)
CONTROLLED TIMING)
is HIGH during a
may be LOW with no degradation to t
t
t
DW
DW
DATA VALID
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DATA VALID
WE
t
WR
controlled write cycle, this requirement does not
t
DH
(3)
t
OW
t
WR
(6)
(3)
(1, 2, 3, 5, 7)
(1, 2, 5, 7)
t
DH
WP
CW
or (t
.
DATA
VALID
t
WHZ
CHZ
+ t
(6)
(4)
DW
) to allow the
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