SM4M64DT-10 Enhanced Memory Systems, Inc., SM4M64DT-10 Datasheet - Page 8

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SM4M64DT-10

Manufacturer Part Number
SM4M64DT-10
Description
168-pin Enhanced SDRAM DIMM 32MB DIMM
Manufacturer
Enhanced Memory Systems, Inc.
Datasheet
168-pin Enhanced SDRAM DIMM
8MB, 16MB, 32MB DIMM
Common Parameters
Refresh Cycle
Notes:
1.
2.
3.
Read Cycle
Notes:
1.
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095;
Page 8 of 13
Symbol
Symbol
Symbol
t
t
t
t
t
t
t
t
t
t
t
SREX
4096 cycles.
Any time that the refresh period has been exceeded, a minimum of two Auto-Refresh (CBR) commands must be given to “wake up” the device.
Self-Refresh exit is a synchronous operation and begins on the 2
completed until t
Referenced to the time at which the output achieves an open circuit condition, not to output voltage levels.
t
t
t
t
t
t
RCD
RAS
RRD
CCD
REF
OH2
OH1
t
DQZ
HZ2
HZ1
CS
CH
AS
AH
RC
RP
LZ
Command Setup Time
Command Hold Time
Address and Bank Select Setup Time
Address and Bank Select Hold Time
RAS to CAS Delay
Bank Cycle Time
Active Command Period
Precharge Time
Bank to Bank Delay Time
CAS to CAS Delay Time (Same Bank)
Refresh Period
Self Refresh Exit Time
Data Out Hold Time CL = 2,3
Data Out Hold Time CL = 1
Data Out to Low Impedance
Data Out to High Impedance CL = 2, 3
Data Out to High Impedance CL = 1
DQM Data Out Disable Latency
RC
is satisfied once the Self-Refresh Exit command is registered.
Parameter
Parameter
Parameter
http://www.edram.com
2CLK+t
37.5
22.5
Min
Min
Min
7.5
15
15
15
2
1
2
1
3
2
0
2
-
-
-
nd
RC
positive clock edge after CKE returns high. Self-Refresh Exit is not
7.5
7.5
7.5
120,000
120,000
Max
Max
Max
7.5
4.5
64
-
-
-
-
-
-
-
-
-
-
-
-
-
The information contained herein is subject to change without notice.
2CLK+t
Min
Min
Min
2.5
2.5
20
50
30
20
20
10
1999 Enhanced Memory Systems. All rights reserved.
1
1
3
2
0
2
-
-
-
RC
10
10
10
120,000
120,000
Max
Max
Max
64
Preliminary Data Sheet
8
5
-
-
-
-
-
-
-
-
-
-
-
-
-
Units
Units
Units
CLK
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Revision 3.1
Notes
Notes
Notes
1, 2
3
1
1

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