ACS8510REV2.1 Semtech Corporation, ACS8510REV2.1 Datasheet - Page 16

• Manufacturer Part Number: ACS8510REV2.1
• Description: Synchronous Equipment Timing Source for Sonet or SDH Network Elements
• Manufacturer: Semtech Corporation

Table 7. Amplitude and Frequency Values for Jitter Tolerance
Table 7. Amplitude and Frequency Values for Jitter Tolerance
Frame Sync and Multi-Frame Sync Clocks (Part of
Frame Sync and Multi-Frame Sync Clocks (Part of
T T T T T
(for inputs supporting G.783 compliant sources)
Table 7. Amplitude and Frequency Values for Jitter Tolerance
Table 7. Amplitude and Frequency Values for Jitter Tolerance
Table 7. Amplitude and Frequency Values for Jitter Tolerance
between
cnfg_differential_outputs register, outputs T
and T
compatible.
Frame Sync and Multi-Frame Sync Clocks (Part of
Frame Sync and Multi-Frame Sync Clocks (Part of
Frame Sync and Multi-Frame Sync Clocks (Part of
Frame Sync (8 kHz) and Multi-Frame Sync
(2 kHz) clocks are provided on outputs T
(FrSync) and T
MFrSync clocks have a 50:50 mark space ratio.
These are driven from the T
synchronized with their counterparts in a second
ACS8510 device (if used), using the technique
described later.
Revision 2.00/September 2003
ADVANCED COMMUNICATIONS
Figure 4. Minimum Input Jitter Tolerance (DS1/E1)
Figure 4. Minimum Input Jitter Tolerance (DS1/E1)
O U T 0
O U T 0
O U T 0
Figure 4. Minimum Input Jitter Tolerance (DS1/E1)
Figure 4. Minimum Input Jitter Tolerance (DS1/E1)
Figure 4. Minimum Input Jitter Tolerance (DS1/E1)
O U T 0
O U T 0
Peak-to-peak jitter and wander amplitude (log
Peak-to-peak jitter and wander amplitude (log
scale)
scale)
) ) ) ) )
O7
can be made to be LVDS or PECL
A1
A1
A2
A2
devices).
O11
f1
f1
(MFrSync). The FrSync and
T
T
T
T
T
D 1
D 1
D 1
D 1
D
p y
p y
p y
p y
p y
E1
E1
E1
E1
E
S
S
S
S
S
1
1
e
e
e
e
e
Semtech Corp.
G
G
G
G
G
R
R
R
R
R
OUT0
T I
T I
T I
T I
T I
1 -
1 -
1 -
1 -
1 -
U
U
U
U
U
S
S
S
S
S
2
2
2
f2
f2
2
2
p
p
p
4
4
4
p
p
4
4
Using
G
G
G
G
G
clock. They are
e
e
e
e
e
4
4
4
4
4
8 .
8 .
8 .
8 .
8 .
. c
. c
. c
. c
. c
C -
C -
C -
C -
C -
2
2
2
2
2
O
O
O
O
O
3
3
3
3
3
R
R
R
R
R
E
E
E
E
E
f3
f3
the
A
A
A
A
A
(
(
(
(
(
A1
A1
A1
A 1
A
1
O10
I U
I U
I U
I U
I U
5
m
m
m
m
m
5 .
1
O6
p
p
p
p
p
p
p
p
p
p
16
i l
i l
i l
i l
i l
k
k
k
k
k
u t
u t
u t
u t
u t
p -
p -
p -
p -
p -
Low Jitter Multiple E1/DS1 Outputs
Low Jitter Multiple E1/DS1 Outputs
Low Jitter Multiple E1/DS1 Outputs
Low Jitter Multiple E1/DS1 Outputs
Low Jitter Multiple E1/DS1 Outputs
This feature added to Rev2.1 is activated using
the cnfg_control1 register. This sends a fre-
quency of twice the Dig2 rate (see reg addr 39h,
bits 7:6) to the APLL instead of the normal
77.76MHz. For this feature to be used, the Dig2
rate must only be set to 12352kHz/16384kHz
using the cnfg_T0_output_frequencies register.
The normal OC3 rate outputs are then replaced
with E1/DS1 multiple rates. The E1(SONET)/
DS1(SDH) selection is made in the same way as
for Dig2 using the cnfg_T0_output_enable reg-
ister. Table 9 shows the relationship between
primary output frequencies and the correspond-
ing output in E1/DS1 mode, and which output
they are available from.
d
d
d
d
d
) k
) k
) k
) k
) k
Jitter and wander frequency (log scale)
Jitter and wander frequency (log scale)
e
e
e
e
e
0
A2
A2
A2
A 2
A
0
2 .
1 .
ACS8510 Rev2.1 SETS
2
f4
f4
F1
F1
F1
F1
F
1
2
1
0
0
2
5
F2
F2
F2
F2
F
0
4 .
F
F
F
F
F
2
e r
e r
e r
0
e r
e r
k
q
q
q
q
q
H ( ) z
H ( ) z
H ( ) z
H ( ) z
H (
u
u
u
u
u
) z
e
e
e
e
e
n
n
n
1
n
n
F3
F3
F3
F3
F
8
8
y c
y c
y c
y c
y c
3
k
k
1
4
F4
F4
F4
F4
F
0
0
4
0
k
k
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FINAL