USBN9604 National Semiconductor, USBN9604 Datasheet - Page 55
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USBN9604
Manufacturer Part Number
USBN9604
Description
USBN9603/USBN9604 Universal Serial Bus Full Speed Node Controller with Enhanced DMA Support
Manufacturer
National Semiconductor
Datasheet
1.USBN9604.pdf
(60 pages)
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8.0 Device Characteristics
8.5 PARALLEL INTERFACE TIMING (MODE1-0 = 01
(3.0V< V
Note: The setup and hold times t
Both signals may switch at the same time.
Symbol
t
t
t
t
t
t
t
t
t
t
WHAH
WHCH
DSWH
DHWH
1. Clock Internal: CKI = 48 MHz on this device
2. Memory Clock: MCLK = CKI/4 = 12 MHz
RHDZ
AHAL
ALRH
RDLV
CLAL
AVAL
t
t
t
CC
WL
AH
RL
< 5.5V, 0˚C < TA< +70˚C, unless otherwise specified)
ALE High Time
Chip Select Low to ALE Low
Address Valid to ALE Low
Address Hold after ALE Low
ALE Low to RD High
Read Low to Data Valid
Data Hold after Read High
Read Pulse Width
Write High to next ALE High
Write High to CS High
Write Pulse Width
Data Setup to WR High
Data Hold after WR High
D7-0 Input
CS
WR
A0
Parameter
Figure 26. Non-Multiplexed Mode Write Timing
1
(Continued)
AS
t
AS
(Consecutive Write Cycles Shown)
and t
2
AH
t
are defined relative to the first transition of either CS or WR.
WW
t
Valid
Conditions
C
C
C
C
C
C
C
C
C
C
C
C
C
DS
L
L
L
L
L
L
L
L
L
L
L
L
L
B
= 50 pF
= 50 pF
= 50 pF
= 50 pF
= 50 pF
= 50 pF
= 50 pF
= 50 pF
= 50 pF
= 50 pF
= 50 pF
= 50 pF
= 50 pF
)
55
t
t
DH
AH
t
WC
3/MCLK
3/MCLK
1/CKI
1/CKI
1/CKI
1/CKI
Min
10
10
10
2
5
5
Valid
Typ
20
Max
30
Units
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
nS
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