ADP3152AR Analog Devices, ADP3152AR Datasheet - Page 6
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ADP3152AR
Manufacturer Part Number
ADP3152AR
Description
5-Bit Programmable Synchronous Switching Regulator Controller for Pentium II Processor
Manufacturer
Analog Devices
Datasheet
1.ADP3152AR.pdf
(12 pages)
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ADP3152
APPLICATION INFORMATION
The ADP3152 uses a current-mode, constant-off-time control
technique to switch a pair of external N-channel MOSFETs in
a synchronous rectified buck converter application. Due to the
constant-off-time operation, no slope compensation is needed.
A unique feature of the constant-off-time control technique is
that the converter’s frequency becomes a function of the ratio of
input voltage to output voltage. The off time is determined by
the value of the external capacitor connected to the C
The on time varies in such a way that a regulated output volt-
age is maintained.
The output voltage is sensed by an internal voltage divider that
is connected to the Sense– pin. A voltage-error amplifier g
compares the values of the divided output voltage with a refer-
ence voltage. The reference voltage is set by an onboard 5-bit
DAC, which reads the code present at the voltage identification
(VID) pins and converts it to a precise value between 600 mV
and 1.167 V. Refer to Table I for the output voltage vs. VID pin
code information.
During continuous-inductor-current mode of operation, the
voltage-error amplifier g
are the main control elements. During the on time of the high
side MOSFET, the current comparator CMPI monitors the
voltage between the Sense+ and Sense– pins. When the voltage
level between the two pins reaches the threshold level V
high side drive output is switched to zero, which turns off the
high side MOSFET. The timing capacitor C
at a rate determined by the off time controller. In order to
maintain a ripple current in the inductor, which is independent
of the output voltage, the discharge current is made propor-
tional to the value of the output voltage (measured at the
Sense– pin). While the timing capacitor is discharging, the low
side drive output goes high, turning on the low side MOSFET.
When the voltage level on the timing capacitor has discharged
to the threshold voltage level V
the SR flip-flop. The output of the flip-flop forces the low side
drive output to go low and the high side drive output to go high.
As a result, the low side switch is turned off and the high side
switch is turned on. The sequence is then repeated. As the load
current increases, the output voltage starts to decrease. This
Figure 13. Closed-Loop Test Circuit for Accuracy
1.2V
4700pF
1k
CODE
5-BIT
100k
VID0–
VID4
SD
CMP
C
AGND
OP27
T
m
0.1 F
ADP3152
and the current comparator CMPI
SENSE+
SENSE–
DRIVE2
DRIVE1
PGND
T2
V
CC
, comparator CMPT resets
12V
+
1 F
T
V
is now discharged
OUT
0.1 F
T1
T
, the
pin.
m
–6–
causes an increase in the output of the voltage-error amplifier,
which, in turn, leads to an increase in the current comparator
threshold V
VID4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
To prevent cross conduction of the external MOSFETs, feed-
back is incorporated to sense the state of the driver output pins.
Before the low side drive output can go high, the high side drive
output must be low. Likewise, the high side drive output is
unable to go high while the low side drive output is high.
Power Good
The ADP3152 has an internal monitor which monitors the
output voltage and drives the PWRGD pin of the device. This
pin is an open drain output whose high level (when connected
to a pull-up resistor) indicates that the output voltage has been
within a 5% regulation band of the targeted value for more
than 500 s. The PWRGD pin will go low if the output is out-
side the regulation band for more than 500 s.
Output Crowbar
An added feature of using an N-channel MOSFET as the syn-
chronous switch is the ability to crowbar the output with the
same MOSFET. If the output voltage is 15% greater than the
desired regulated value, the ADP3152 will turn on the lower
MOSFET, which will current-limit the source power supply or
blow its fuse, pull down the output voltage, and thus save the
VID3
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
T1,
Table I. Output Voltage vs. VID Code
thus tracking the load current.
VID2
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
VID1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
VID0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
VOUT
1.80
1.80
1.80
1.80
1.80
1.80
1.80
1.80
1.80
1.80
1.80
1.85
1.90
1.95
2.00
2.05
Shutdown
2.10
2.20
2.30
2.40
2.50
2.60
2.70
2.80
2.90
3.00
3.10
3.20
3.30
3.40
3.50
REV. 0