ADP3163 Analog Devices, ADP3163 Datasheet - Page 4

• Manufacturer Part Number: ADP3163
• Description: 5-Bit Programmable 2-/3-Phase Synchronous Buck Controller
• Manufacturer: Analog Devices

ADP3163
Pin
1–5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
100nF
100
5-BIT CODE
Name
VID4 –
VID0
SHARE
COMP
GND
FB
CT
PWRGD
CS+
CS–
PGND
PC
PWM3
PWM2
PWM1
REF
VCC
AD820
10
1
2
3
4
5
6
7
8
9
Function
Voltage Identification DAC Inputs. These pins are pulled up to an internal 3 V reference, providing a
Logic 1 if left open. The DAC output programs the FB regulation voltage from 1.1 V to 1.85 V. Leaving all five
DAC inputs open results in the ADP3163 going into a “No CPU” mode, shutting off its PWM outputs.
Current Sharing Output. This pin is connected to the SHARE pins of other ADP3163s in multiple VRM sys-
tems to ensure proper current sharing between the converters. The voltage at this output programs the output
current control level between CS+ and CS–.
Error Amplifier Output and Compensation Point.
Ground. FB, REF and the VID DAC of the ADP3163 are referenced to this ground. This is a low current ground
that can also be used as a return for the FB pin in remote voltage sensing applications.
Feedback Input. Error amplifier input for remote sensing of the output voltage.
External capacitor CT connection to ground sets the frequency of the device.
Open drain output that signals when the output voltage is outside of the proper operating range or when a phase
is not supplying current even if the output voltage is in specification.
Current Sense Positive Node. Positive input for the current comparator. The output current is sensed as a volt-
age at this pin with respect to CS–.
Current Sense Negative Node. Negative input for the current comparator.
Power Ground. All internal biasing and logic output signals of the ADP3163 are referenced to this ground.
Phase Control Input. This logic-level input determines the number of active phases and the duty cycle limit of
each phase.
Logic-Level Output for the Phase 3 Driver.
Logic-Level Output for the Phase 2 Driver.
Logic-Level Output for the Phase 1 Driver.
3.0 V Reference Output.
Supply Voltage for the ADP3163.
VID4
VID3
VID2
VID1
VID0
SHARE
COMP
GND
FB
CT
ADP3163
PWRGD
PWM1
PWM2
PWM3
PGND
VCC
REF
CS–
CS+
PC
20
19
18
17
16
15
14
13
12
11
1.2V
20k
V
FB
1 F
PIN FUNCTION DESCRIPTIONS
100nF
12V
PC
REF
GND
Table I. PWM Outputs vs. Phase Control Code
PWM3
ON
OFF
PWM2
ON
ON
PWM1
ON
ON
Maximum
Duty Cycle
33%
50%