AAT2500 Analogic Corporation, AAT2500 Datasheet - Page 19

• Manufacturer Part Number: AAT2500
• Manufacturer: Analogic Corporation

Thermal Calculations
There are three types of losses associated with the
AAT2500 step-down converter: switching losses,
conduction losses, and quiescent current losses.
Conduction losses are associated with the R
characteristics of the power output switching
devices. Switching losses are dominated by the
gate charge of the power output switching devices.
At full load, assuming continuous conduction mode
(CCM), a simplified form of the step-down convert-
er and LDO losses is given by:
I
rent and I
term t
converter switching losses.
For the condition where the buck converter is in
dropout at 100% duty cycle, the total device dissi-
pation reduces to:
Since R
losses all vary with input voltage, the total losses
should be investigated over the complete input
voltage range.
P
2500.2005.08.1.9
P
QBUCK
TOTAL
TOTAL
+ (t
=
sw
+ (I
= I
I
is the step-down converter quiescent cur-
OBUCK
sw
is used to estimate the full load step-down
DS(ON)
OBUCK
· F · I
QBUCK
QLDO
2
· (R
OBUCK
2
, quiescent current, and switching
DSON(HS)
+ I
is the LDO quiescent current. The
· R
QLDO
+ I
DSON(HS)
QBUCK
· V
) · V
OBUCK
+ I
+ I
IN
V
QLDO
IN
+ R
OLDO
) · V
DSON(LS)
· (V
IN
+ I
· [V
IN
OLDO
- V
IN
· (V
- V
OLDO
OBUCK
IN
- V
1MHz Step-Down Converter/LDO Regulator
)
DS(ON)
])
OLDO
)
Given the total losses, the maximum junction tem-
perature can be derived from the θ
TDFN33-12 package which is 50°C/W.
PCB Layout
The following guidelines should be used to ensure
a proper layout.
1. The input capacitor C2 should connect as
2. The output capacitor and inductor should be
3. The feedback trace should be separate from
4. The resistance of the trace from the load return
5. For good thermal coupling, PCB vias are
6. LDO bypass capacitor (C5) should be connected
closely as possible to VP and PGND, as shown
in Figure 4.
connected as closely as possible. The connec-
tion of the inductor to the LX pin should also be
as short as possible.
any power trace and connect as closely as
possible to the load point. Sensing along a
high-current load trace will degrade DC load
regulation. If external feedback resistors are
used, they should be placed as closely as pos-
sible to the FB pin. This prevents noise from
being coupled into the high impedance feed-
back node.
to GND should be kept to a minimum. This will
help to minimize any error in DC regulation due
to differences in the potential of the internal sig-
nal ground and the power ground.
required from the pad for the TDFN paddle to the
ground plane. The via diameter should be 0.3mm
to 0.33mm and positioned on a 1.2mm grid.
directly between pins 7 (BYP) and 8 (GND)
T
J(MAX)
= P
TOTAL
· Θ
JA
+ T
AAT2500
AMB
JA
for the
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