MCP3021 Microchip Technology, Inc., MCP3021 Datasheet - Page 16

• Manufacturer Part Number: MCP3021
• Description: The Microchip Technology Inc
• Manufacturer: Microchip Technology, Inc.

MCP3021
5.2
The address byte is the first byte received following the
START condition from the master device. The first part
of the control byte consists of a 4-bit device code,
which is set to 1001 for the MCP3021. The device code
is followed by three address bits: A2, A1 and A0. The
default address bits are 101 (contact the Microchip fac-
tory for additional address bit options).The address bits
allow up to eight MCP3021 devices on the same bus
and are used to determine which device is accessed.
The eighth bit of the slave address determines if the
master device wants to read conversion data or write to
the MCP3021. When set to a ‘1’, a read operation is
selected. When set to a ‘0’, a write operation is
selected. There are no writable registers on the
MCP3021, therefore, this bit must be set to a ’1’ to
initiate a conversion.
The MCP3021 is a slave device that is compatible with
the 2-wire I
connection diagram is shown in Figure 6-2. Communi-
cation is initiated by the microcontroller (master
device), which sends a START bit followed by the
address byte.
On completion of the conversion(s) performed by the
MCP3021, the microcontroller must send a STOP bit to
stop the communication.
The last bit in the device address byte is the R/W bit.
When this bit is a logic ‘1’, a conversion will be exe-
cuted. Setting this bit to logic ‘0’ will also result in an
“acknowledge” (ACK) from the MCP3021, with the
device then releasing the bus. This can be used for
device polling (refer to Section 6.3, “Device Polling”).
FIGURE 5-2:
DS21805A-page 16
1
Contact Microchip for additional address bits.
START
1
Device Addressing
Device Code
2
0
C serial interface protocol. A hardware
SLAVE ADDRESS
0
Device Addressing.
1
Address Bits
1
READ/WRITE
0
1
1
R/W
A
5.3
This section will describe the details of communicating
with the MCP3021 device. Initiating the sample and
hold acquisition, reading the conversion data and
executing multiple conversions will be discussed.
5.3.1
The acquisition and conversion of the input signal
begins with the falling edge of the R/W bit of the
address byte. At this point, the internal clock initiates
the sample, hold and conversion cycle, all of which are
internal to the ADC.
FIGURE 5-3:
Address Byte.
FIGURE 5-4:
Continuous Conversions.
SDA
SCL
SDA
SCL
Executing a Conversion
Start
D6
Bit
17 18 19 20 21 22 23 24 25 26
INITIATING THE SAMPLE AND
HOLD
1
1
D5
Device bits
0
2
D4 D3 D2
Initiating the Conversion,
Initiating the Conversion,
Lower Data Byte (n)
t
ACQ
3
initiated here
0
t
ACQ
Address Byte
initiated here
2003 Microchip Technology Inc.
4
+ t
1
+ t
CONV
Address bits
D1 D0 X
CONV
A2 A1 A0
5
is
6
is
7
R/W
X
8
9