OPA2607 Burr-Brown, OPA2607 Datasheet - Page 10

• Manufacturer Part Number: OPA2607
• Description: Dual / High Output / Current-Feedback OPERATIONAL AMPLIFIER
• Manufacturer: Burr-Brown

tion for the op amp voltage noise alone. This reflects the
noise added to the output by the inverting current noise times
the feedback resistor. If the feedback resistor is reduced in
high-gain configurations (as suggested previously), the total
input referred voltage noise given by Equation 5 will ap-
proach just the 1.7nV/ Hz of the op amp itself. For example,
going to a gain of +20 using R
input referred noise of 2.0nV/ Hz .
DC ACCURACY AND OFFSET CONTROL
A current-feedback op amp like the OPA2607 provides
exceptional bandwidth in high gains, giving fast pulse set-
tling but only moderate DC accuracy. The typical specifica-
tions show an input offset voltage comparable to high-speed
voltage-feedback amplifiers. However, the two input bias
currents are somewhat higher and are unmatched. Whereas
bias current cancellation techniques are very effective with
most voltage-feedback op amps, they do not generally re-
duce the output DC offset for wideband current-feedback op
amps. Since the two input bias currents are unrelated in both
magnitude and polarity, matching the source impedance
looking out of each input to reduce their error contribution
to the output is ineffective. Evaluating the configuration of
Figure 1, using worst case +25 C input offset voltage and
the two input bias currents, gives a worst case output offset
range equal to:
THERMAL ANALYSIS
Maximum desired junction temperature will set the maxi-
mum allowed internal power dissipating. In no case should
the maximum junction temperature exceed 175 C. The op-
erating junction temperature is given by:
where T
power dissipation as calculated below, and
age thermal resistance shown in the specifications.
The total internal power dissipation of a single amplifier,
assuming bipolar supplies ( V
where I
average output current, I
put current, and R
absolute worst case conditions, with V
becomes:
=
= 56.0mV
= 107mV
(NG • V
(8 • 7mV)
Q
A
is the quiescent supply current, I
is the ambient temperature, P
P
where NG = non-inverting signal gain
D
®
OS(MAX)
OPA2607
2
P
2.4mV
V I
D
L
S Q
(12 A • 25
is the load seen by the output. Under
T
)
2
J
V I
O(RMS)
V I
S Q
(I
T
48.4mV
S O AVE
BN
A
(
• R
S
is the root-mean-square out-
V
P
), is:
F
D JA
S
2
S
• 8)
= 750
/2 • NG)
)
/
–
4
I
R
2
O RMS
O
L
(
(40 A • 1.21k )
= V
D
will give a total
S
)
is the average
JA
R
/2, Equation 7
(I
O(AVE)
L
BI
is the pack-
• R
F
is the
)
(6)
(7)
(8)
10
The ADSL Upstream Driver shown on the front page will be
used as an example of these calculations. The ADSL
(G.DMT) standard uses a spectrally-efficient coding tech-
nique, which produces a near-Gaussian output voltage distri-
bution. Under these conditions, I
The maximum allowed crest factor in this standard is
CF = 5.33Vpk/Vrms. We now calculate for each amplifier
individually:
Now calculate the typical junction temperature of both
channels of the OPA2607H (PSO-8
based on Equations 6 and 7:
The junction temperature of this example is well below
175 C absolute maximum because the PSO-8 power pack-
age has such a low thermal impedance when properly
connected to the –V
Guidelines section). To help illustrate this point, the regular
SO-8 package (OPA2607U) gives T
same conditions.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high-frequency
amplifier like the OPA2607 requires careful attention to
board layout parasitics and external component types. Rec-
ommendations that will optimize performance include:
a) Minimize parasitic capacitance to any AC ground for
all of the signal I/O pins. Parasitic capacitance on the output
and inverting input pins can cause instability. On the non-
inverting input it can react with the source impedance to
cause unintentional bandlimiting. To reduce unwanted ca-
pacitance, a window around the signal I/O pins should be
opened in all of the ground and power planes around those
pins. Otherwise, ground and power planes should be unbro-
ken elsewhere on the board.
b) Minimize the distance (< 0.25") from the power supply
pins to high frequency 0.1 F decoupling capacitors. At the
device pins, the ground and power plane layout should not
be in close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance between
the pins and the decoupling capacitors. The power supply
R
L
I
I
I
O PK
O RMS
O AVE
P
T
141
(
(
(
D
J
78 7
)
2
.
120
)
)
85
2 12
0 69
.
(
V
12
0 8
I
C
O PK
R
W
O PK
.
C
CF
(
V
100
V
L
(
I
S
0 8
0 69
O RMS
)
.
.
)
20 2
16
(
power plane (see the Board Layout
2
/
.
mA
W
38
2
135
mA
)
5 33
Vp p
•
141
.
50
mA
20 2
) –
1 21
. k
.
C W
/
25 3
mA
/
2
25 3
O(AVE)
.
J
.
mA
135
= 171 C under the
mA
348
mA
2
2
= 0.8 I
141
Package)
O(RMS)
(10)
(9)
.