AD9501 Analog Devices, AD9501 Datasheet - Page 5

• Manufacturer Part Number: AD9501
• Description: Digitally Programmable Delay Generator
• Manufacturer: Analog Devices

REV. A
THEORY OF OPERATION
The AD9501 is a digitally programmable delay device. Its
function is to provide a precise incremental delay between input
and output, proportional to an 8-bit digital word applied to its
delay control port. Incremental delay resolution is 10 ps at the
minimum full-scale range of 2.5 ns. Digital delay data inputs,
latch, trigger and reset are all TTL/CMOS compatible. Output
is TTL-compatible.
Refer to the block diagram of the AD9501.
Inside the unit, there are three main subcircuits: a linear ramp
generator, an 8-bit digital-to-analog converter (DAC) and a
voltage comparator. The rising edge of the input (TRIGGER)
pulse initiates the delay cycle by triggering the ramp generator.
The voltage comparator monitors the ramp voltage and switches
the delayed output (Pin 10) HIGH when the ramp voltage
crosses the threshold set by the DAC output voltage. The DAC
threshold voltage is programmed by the user with digital inputs.
Figure 1. AD9501 Internal Timing
–5–
Figure 1, the AD9501 Internal Timing diagram, illustrates in
detail how the delay is determined. Minimum Delay (t
sum of Trigger Circuit delay, Ramp Generator delay, and
Comparator delay.
The Trigger Circuit delay and Comparator delay are fixed;
Ramp Generator delay is a variable affected by the rate of
change of the linear ramp and (to a lesser degree) the value of
the offset voltage described below.
Maximum Delay is the sum of Minimum Delay (t
Scale Program Delay (t
Ramp Generator delay is the time required for the ramp to slew
from its reset voltage to the most positive DAC reference
voltage (00
18 mV (with OFFSET ADJUST open) or 34 mV (OFFSET
ADJUST grounded).
H
). The difference in these two voltages is nominally
DFS
).
AD9501
PD
) and Full-
PD
) is the