AD9822 Analog Devices, AD9822 Datasheet - Page 3

• Manufacturer Part Number: AD9822
• Description: Complete 14-Bit CCD/CIS Signal Processor
• Manufacturer: Analog Devices

REV. A
NOTES
1
2
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS
Parameter
LOGIC INPUTS
LOGIC OUTPUTS
Specifications subject to change without notice.
TIMING SPECIFICATIONS
Parameter
CLOCK PARAMETERS
SERIAL INTERFACE
DATA OUTPUT
Specifications subject to change without notice.
Linear input signal range is from 2 V to 4 V when the CCD’s reference level is clamped to 4 V by the AD9822’s input clamp.
The PGA Gain is approximately “linear in dB” and follows the equation:
3-Channel Pixel Rate
1-Channel Pixel Rate
ADCCLK Pulsewidth
CDSCLK1 Pulsewidth
CDSCLK2 Pulsewidth
CDSCLK1 Falling to CDSCLK2 Rising
ADCCLK Falling to CDSCLK2 Rising
CDSCLK2 Rising to ADCCLK Rising
CDSCLK2 Falling to ADCCLK Falling
CDSCLK2 Falling to CDSCLK1 Rising
ADCCLK Falling to CDSCLK1 Rising
Aperture Delay for CDS Clocks
Maximum SCLK Frequency
SLOAD to SCLK Setup Time
SCLK to SLOAD Hold Time
SDATA to SCLK Rising Setup Time
SCLK Rising to SDATA Hold Time
SCLK Falling to SDATA Valid
Output Delay
3-State to Data Valid
Output Enable High to 3-State
Latency (Pipeline Delay)
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
High Level Output Voltage
Low Level Output Voltage
High Level Output Current
Low Level Output Current
RESET TRANSIENT
1V TYP
(T
(T
C
MIN
L
MIN
= 10 pF, unless otherwise noted.)
to T
Symbol
V
V
I
I
C
V
V
I
I
to T
IH
IL
OH
OL
IH
IL
OH
OL
IN
MAX
MAX
, AVDD = 5 V, DRVDD = 5 V)
, AVDD = 5 V, DRVDD = 5 V, CDS Mode, f
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
f
t
t
t
t
t
t
t
t
PRA
PRB
ADCLK
C1
C2
C1C2
ADC2
C2ADR
C2ADF
C2C1
ADC1
AD
SCLK
LS
LH
DS
DH
RDV
OD
DV
HZ
Gain
Min
2.0
4.5
–3–
[
2V p-p MAX INPUT SIGNAL RANGE
1
4V SET BY INPUT CLAMP (3V OPTION ALSO AVAILABLE)
4 7
. [
5 7
Min
67
80
30
10
10
0
0
0
30
30
0
10
10
10
10
10
10
.
63 – G
63
]
]
where G is the register value. See Figure 13.
Typ
10
10
10
50
50
ADCCLK
Typ
40
40
2
8
10
10
3 (Fixed)
= 15 MHz, f
CDSCLK1
Max
0.8
0.1
Max
= f
CDSCLK2
= 5 MHz,
AD9822
Unit
V
V
pF
V
V
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Cycles
A
A
A
A