AD9843A Analog Devices, AD9843A Datasheet - Page 9

• Manufacturer Part Number: AD9843A
• Description: Complete 10-Bit 20 MSPS CCD Signal Processor
• Manufacturer: Analog Devices

CCD-MODE AND AUX-MODE TIMING
OUTPUT
SIGNAL
CLPOB
CLPDM
DATACLK
DATA
PBLK
OUTPUT
DATACLK
SIGNAL
CCD
OUTPUT
SIGNAL
DATA
VIDEO
CCD
SHP
SHD
DATA
NOTES:
1. CLPOB AND CLPDM WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING CLPDM AND/OR CLPOB.
2. PBLK SIGNAL IS OPTIONAL.
3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS 9 DATACLK CYCLES.
NOTES:
1. RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE.
2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES.
EFFECTIVE PIXELS
EFFECTIVE PIXEL DATA
t
ID
t
S1
N–10
N–10
t
INH
t
OD
t
N
OD
N
t
ID
t
ID
N–9
OPTICAL BLACK PIXELS
t
S2
N–9
N+1
OB PIXEL DATA
N+1
t
H
t
H
t
CP
t
N–8
CP
N–8
N+2
N+2
HORIZONTAL
BLANKING
N+8
DUMMY PIXELS
DUMMY BLACK
N–1
N–1
N+9
N+9
EFFECTIVE PIXELS
EFFECTIVE DATA
AD9843A
N
N
N+10