AD9845 Analog Devices, AD9845 Datasheet - Page 16

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AD9845

Manufacturer Part Number
AD9845
Description
Complete 12-Bit 30 MSPS CCD Signal Processor
Manufacturer
Analog Devices
Datasheet

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AD9845A
D10
X
D10 D9
X
D10
X
Control Register Bit D3 must be set High (PxGA Enable) to use the PxGA Gain Registers.
Must be set to zero.
When D3 = 0 (PxGA disabled) the PxGA gain is fixed to 4 dB.
Data Out
0 Enable
1 Three-State
D9
X
D9
X
D8
X
D8
X
D8 D7 D6
0
Table VI. PxGA Gain Registers for Gain0, Gain1, Gain2, Gain3 (Default Value x000)
0
MSB
D7
0
0
0
1
1
1 Falling Edge Trigger 1 Active High 1 Active High
DATACLK
0 Rising Edge Trigger 0 Active Low 0 Active Low
D7
X
Table IV. Clamp Level Register Contents (Default Value x080)
Table V. Control Register Contents (Default Value x000)
D6
0
0
0
1
1
D6
X
D5
0
0
0
1
1
MSB
D5
0
0
1
1
CLP/PBLK
D5
D4
0
0
0
1
1
D4
1
0
1
0
D3
1
1
0
0
0
SHP/SHD
D4
D3
1
0
1
0
D2
0
0
0
1
1
D2
1
0
1
0
D1
0
0
1
1
1
PxGA
D3
0 Disable 0
1 Enable 0
D1
1
0
1
0
LSB
D0
0
1
0
0
1
Color Steering Modes
D2 D1 D0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
LSB
D0
1
0
1
0
0 Steering Disabled
1 Mosaic Separate
0 Interlace
1 3-Color
0 4-Color
1 VD Selected
0 Mosaic Repeat
1 User Specified
Clamp Level (LSB)
0
1
2
254
255
Gain (dB)
+10.0
+4.3
+4.0
–2.0

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